Commit 50e76151 authored by Paul Kocialkowski's avatar Paul Kocialkowski Committed by Mauro Carvalho Chehab

media: platform: Add Cedrus VPU decoder driver

This introduces the Cedrus VPU driver that supports the VPU found in
Allwinner SoCs, also known as Video Engine. It is implemented through
a V4L2 M2M decoder device and a media device (used for media requests).
So far, it only supports MPEG-2 decoding.

Since this VPU is stateless, synchronization with media requests is
required in order to ensure consistency between frame headers that
contain metadata about the frame to process and the raw slice data that
is used to generate the frame.

This driver was made possible thanks to the long-standing effort
carried out by the linux-sunxi community in the interest of reverse
engineering, documenting and implementing support for the Allwinner VPU.
Signed-off-by: default avatarPaul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
[hans.verkuil@cisco.com: dropped obsolete MEDIA_REQUEST_API from Kconfig]
Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent a20625fb
......@@ -663,6 +663,13 @@ L: linux-crypto@vger.kernel.org
S: Maintained
F: drivers/crypto/sunxi-ss/
ALLWINNER VPU DRIVER
M: Maxime Ripard <maxime.ripard@bootlin.com>
M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
L: linux-media@vger.kernel.org
S: Maintained
F: drivers/staging/media/sunxi/cedrus/
ALPHA PORT
M: Richard Henderson <rth@twiddle.net>
M: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
......
......@@ -31,6 +31,8 @@ source "drivers/staging/media/mt9t031/Kconfig"
source "drivers/staging/media/omap4iss/Kconfig"
source "drivers/staging/media/sunxi/Kconfig"
source "drivers/staging/media/tegra-vde/Kconfig"
source "drivers/staging/media/zoran/Kconfig"
......
......@@ -5,5 +5,6 @@ obj-$(CONFIG_SOC_CAMERA_IMX074) += imx074/
obj-$(CONFIG_SOC_CAMERA_MT9T031) += mt9t031/
obj-$(CONFIG_VIDEO_DM365_VPFE) += davinci_vpfe/
obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
obj-$(CONFIG_VIDEO_SUNXI) += sunxi/
obj-$(CONFIG_TEGRA_VDE) += tegra-vde/
obj-$(CONFIG_VIDEO_ZORAN) += zoran/
config VIDEO_SUNXI
bool "Allwinner sunXi family Video Devices"
depends on ARCH_SUNXI || COMPILE_TEST
help
If you have an Allwinner SoC based on the sunXi family, say Y.
Note that this option doesn't include new drivers in the
kernel: saying N will just cause Kconfig to skip all the
questions about Allwinner media devices.
if VIDEO_SUNXI
source "drivers/staging/media/sunxi/cedrus/Kconfig"
endif
obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += cedrus/
config VIDEO_SUNXI_CEDRUS
tristate "Allwinner Cedrus VPU driver"
depends on VIDEO_DEV && VIDEO_V4L2 && MEDIA_CONTROLLER
depends on HAS_DMA
depends on OF
select SUNXI_SRAM
select VIDEOBUF2_DMA_CONTIG
select V4L2_MEM2MEM_DEV
help
Support for the VPU found in Allwinner SoCs, also known as the Cedar
video engine.
To compile this driver as a module, choose M here: the module
will be called sunxi-cedrus.
obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o
sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o cedrus_mpeg2.o
Before this stateless decoder driver can leave the staging area:
* The Request API needs to be stabilized;
* The codec-specific controls need to be thoroughly reviewed to ensure they
cover all intended uses cases;
* Userspace support for the Request API needs to be reviewed;
* Another stateless decoder driver should be submitted;
* At least one stateless encoder driver should be submitted.
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Cedrus VPU driver
*
* Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
* Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
* Copyright (C) 2018 Bootlin
*
* Based on the vim2m driver, that is:
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* Pawel Osciak, <pawel@osciak.com>
* Marek Szyprowski, <m.szyprowski@samsung.com>
*/
#ifndef _CEDRUS_H_
#define _CEDRUS_H_
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-mem2mem.h>
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-contig.h>
#include <linux/platform_device.h>
#define CEDRUS_NAME "cedrus"
#define CEDRUS_CAPABILITY_UNTILED BIT(0)
enum cedrus_codec {
CEDRUS_CODEC_MPEG2,
CEDRUS_CODEC_LAST,
};
enum cedrus_irq_status {
CEDRUS_IRQ_NONE,
CEDRUS_IRQ_ERROR,
CEDRUS_IRQ_OK,
};
struct cedrus_control {
u32 id;
u32 elem_size;
enum cedrus_codec codec;
unsigned char required:1;
};
struct cedrus_mpeg2_run {
const struct v4l2_ctrl_mpeg2_slice_params *slice_params;
const struct v4l2_ctrl_mpeg2_quantization *quantization;
};
struct cedrus_run {
struct vb2_v4l2_buffer *src;
struct vb2_v4l2_buffer *dst;
union {
struct cedrus_mpeg2_run mpeg2;
};
};
struct cedrus_buffer {
struct v4l2_m2m_buffer m2m_buf;
};
struct cedrus_ctx {
struct v4l2_fh fh;
struct cedrus_dev *dev;
struct v4l2_pix_format src_fmt;
struct v4l2_pix_format dst_fmt;
enum cedrus_codec current_codec;
struct v4l2_ctrl_handler hdl;
struct v4l2_ctrl **ctrls;
struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME];
};
struct cedrus_dec_ops {
void (*irq_clear)(struct cedrus_ctx *ctx);
void (*irq_disable)(struct cedrus_ctx *ctx);
enum cedrus_irq_status (*irq_status)(struct cedrus_ctx *ctx);
void (*setup)(struct cedrus_ctx *ctx, struct cedrus_run *run);
int (*start)(struct cedrus_ctx *ctx);
void (*stop)(struct cedrus_ctx *ctx);
void (*trigger)(struct cedrus_ctx *ctx);
};
struct cedrus_variant {
unsigned int capabilities;
};
struct cedrus_dev {
struct v4l2_device v4l2_dev;
struct video_device vfd;
struct media_device mdev;
struct media_pad pad[2];
struct platform_device *pdev;
struct device *dev;
struct v4l2_m2m_dev *m2m_dev;
struct cedrus_dec_ops *dec_ops[CEDRUS_CODEC_LAST];
/* Device file mutex */
struct mutex dev_mutex;
/* Interrupt spinlock */
spinlock_t irq_lock;
void __iomem *base;
struct clk *mod_clk;
struct clk *ahb_clk;
struct clk *ram_clk;
struct reset_control *rstc;
unsigned int capabilities;
};
extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2;
static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val)
{
writel(val, dev->base + reg);
}
static inline u32 cedrus_read(struct cedrus_dev *dev, u32 reg)
{
return readl(dev->base + reg);
}
static inline dma_addr_t cedrus_buf_addr(struct vb2_buffer *buf,
struct v4l2_pix_format *pix_fmt,
unsigned int plane)
{
dma_addr_t addr = vb2_dma_contig_plane_dma_addr(buf, 0);
return addr + (pix_fmt ? (dma_addr_t)pix_fmt->bytesperline *
pix_fmt->height * plane : 0);
}
static inline dma_addr_t cedrus_dst_buf_addr(struct cedrus_ctx *ctx,
unsigned int index,
unsigned int plane)
{
struct vb2_buffer *buf = ctx->dst_bufs[index];
return buf ? cedrus_buf_addr(buf, &ctx->dst_fmt, plane) : 0;
}
static inline struct cedrus_buffer *
vb2_v4l2_to_cedrus_buffer(const struct vb2_v4l2_buffer *p)
{
return container_of(p, struct cedrus_buffer, m2m_buf.vb);
}
static inline struct cedrus_buffer *
vb2_to_cedrus_buffer(const struct vb2_buffer *p)
{
return vb2_v4l2_to_cedrus_buffer(to_vb2_v4l2_buffer(p));
}
void *cedrus_find_control_data(struct cedrus_ctx *ctx, u32 id);
#endif
// SPDX-License-Identifier: GPL-2.0
/*
* Cedrus VPU driver
*
* Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
* Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
* Copyright (C) 2018 Bootlin
*
* Based on the vim2m driver, that is:
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* Pawel Osciak, <pawel@osciak.com>
* Marek Szyprowski, <m.szyprowski@samsung.com>
*/
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-event.h>
#include <media/v4l2-mem2mem.h>
#include "cedrus.h"
#include "cedrus_dec.h"
#include "cedrus_hw.h"
void cedrus_device_run(void *priv)
{
struct cedrus_ctx *ctx = priv;
struct cedrus_dev *dev = ctx->dev;
struct cedrus_run run = { 0 };
struct media_request *src_req;
unsigned long flags;
run.src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
run.dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
/* Apply request(s) controls if needed. */
src_req = run.src->vb2_buf.req_obj.req;
if (src_req)
v4l2_ctrl_request_setup(src_req, &ctx->hdl);
spin_lock_irqsave(&ctx->dev->irq_lock, flags);
switch (ctx->src_fmt.pixelformat) {
case V4L2_PIX_FMT_MPEG2_SLICE:
run.mpeg2.slice_params = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS);
run.mpeg2.quantization = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION);
break;
default:
break;
}
dev->dec_ops[ctx->current_codec]->setup(ctx, &run);
spin_unlock_irqrestore(&ctx->dev->irq_lock, flags);
/* Complete request(s) controls if needed. */
if (src_req)
v4l2_ctrl_request_complete(src_req, &ctx->hdl);
spin_lock_irqsave(&ctx->dev->irq_lock, flags);
dev->dec_ops[ctx->current_codec]->trigger(ctx);
spin_unlock_irqrestore(&ctx->dev->irq_lock, flags);
}
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Cedrus VPU driver
*
* Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
* Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
* Copyright (C) 2018 Bootlin
*
* Based on the vim2m driver, that is:
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* Pawel Osciak, <pawel@osciak.com>
* Marek Szyprowski, <m.szyprowski@samsung.com>
*/
#ifndef _CEDRUS_DEC_H_
#define _CEDRUS_DEC_H_
extern const struct v4l2_ioctl_ops cedrus_ioctl_ops;
void cedrus_device_work(struct work_struct *work);
void cedrus_device_run(void *priv);
int cedrus_queue_init(void *priv, struct vb2_queue *src_vq,
struct vb2_queue *dst_vq);
#endif
// SPDX-License-Identifier: GPL-2.0
/*
* Cedrus VPU driver
*
* Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
* Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
* Copyright (C) 2018 Bootlin
*
* Based on the vim2m driver, that is:
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* Pawel Osciak, <pawel@osciak.com>
* Marek Szyprowski, <m.szyprowski@samsung.com>
*/
#include <linux/platform_device.h>
#include <linux/of_reserved_mem.h>
#include <linux/of_device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/soc/sunxi/sunxi_sram.h>
#include <media/videobuf2-core.h>
#include <media/v4l2-mem2mem.h>
#include "cedrus.h"
#include "cedrus_hw.h"
#include "cedrus_regs.h"
int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec)
{
u32 reg = 0;
/*
* FIXME: This is only valid on 32-bits DDR's, we should test
* it on the A13/A33.
*/
reg |= VE_MODE_REC_WR_MODE_2MB;
reg |= VE_MODE_DDR_MODE_BW_128;
switch (codec) {
case CEDRUS_CODEC_MPEG2:
reg |= VE_MODE_DEC_MPEG;
break;
default:
return -EINVAL;
}
cedrus_write(dev, VE_MODE, reg);
return 0;
}
void cedrus_engine_disable(struct cedrus_dev *dev)
{
cedrus_write(dev, VE_MODE, VE_MODE_DISABLED);
}
void cedrus_dst_format_set(struct cedrus_dev *dev,
struct v4l2_pix_format *fmt)
{
unsigned int width = fmt->width;
unsigned int height = fmt->height;
u32 chroma_size;
u32 reg;
switch (fmt->pixelformat) {
case V4L2_PIX_FMT_NV12:
chroma_size = ALIGN(width, 16) * ALIGN(height, 16) / 2;
reg = VE_PRIMARY_OUT_FMT_NV12;
cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg);
reg = VE_CHROMA_BUF_LEN_SDRT(chroma_size / 2);
cedrus_write(dev, VE_CHROMA_BUF_LEN, reg);
reg = chroma_size / 2;
cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg);
reg = VE_PRIMARY_FB_LINE_STRIDE_LUMA(ALIGN(width, 16)) |
VE_PRIMARY_FB_LINE_STRIDE_CHROMA(ALIGN(width, 16) / 2);
cedrus_write(dev, VE_PRIMARY_FB_LINE_STRIDE, reg);
break;
case V4L2_PIX_FMT_SUNXI_TILED_NV12:
default:
reg = VE_PRIMARY_OUT_FMT_TILED_32_NV12;
cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg);
reg = VE_SECONDARY_OUT_FMT_TILED_32_NV12;
cedrus_write(dev, VE_CHROMA_BUF_LEN, reg);
break;
}
}
static irqreturn_t cedrus_bh(int irq, void *data)
{
struct cedrus_dev *dev = data;
struct cedrus_ctx *ctx;
ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
if (!ctx) {
v4l2_err(&dev->v4l2_dev,
"Instance released before the end of transaction\n");
return IRQ_HANDLED;
}
v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
return IRQ_HANDLED;
}
static irqreturn_t cedrus_irq(int irq, void *data)
{
struct cedrus_dev *dev = data;
struct cedrus_ctx *ctx;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
enum vb2_buffer_state state;
enum cedrus_irq_status status;
unsigned long flags;
spin_lock_irqsave(&dev->irq_lock, flags);
ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
if (!ctx) {
v4l2_err(&dev->v4l2_dev,
"Instance released before the end of transaction\n");
spin_unlock_irqrestore(&dev->irq_lock, flags);
return IRQ_NONE;
}
status = dev->dec_ops[ctx->current_codec]->irq_status(ctx);
if (status == CEDRUS_IRQ_NONE) {
spin_unlock_irqrestore(&dev->irq_lock, flags);
return IRQ_NONE;
}
dev->dec_ops[ctx->current_codec]->irq_disable(ctx);
dev->dec_ops[ctx->current_codec]->irq_clear(ctx);
src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
if (!src_buf || !dst_buf) {
v4l2_err(&dev->v4l2_dev,
"Missing source and/or destination buffers\n");
spin_unlock_irqrestore(&dev->irq_lock, flags);
return IRQ_HANDLED;
}
if (status == CEDRUS_IRQ_ERROR)
state = VB2_BUF_STATE_ERROR;
else
state = VB2_BUF_STATE_DONE;
v4l2_m2m_buf_done(src_buf, state);
v4l2_m2m_buf_done(dst_buf, state);
spin_unlock_irqrestore(&dev->irq_lock, flags);
return IRQ_WAKE_THREAD;
}
int cedrus_hw_probe(struct cedrus_dev *dev)
{
const struct cedrus_variant *variant;
struct resource *res;
int irq_dec;
int ret;
variant = of_device_get_match_data(dev->dev);
if (!variant)
return -EINVAL;
dev->capabilities = variant->capabilities;
irq_dec = platform_get_irq(dev->pdev, 0);
if (irq_dec <= 0) {
v4l2_err(&dev->v4l2_dev, "Failed to get IRQ\n");
return irq_dec;
}
ret = devm_request_threaded_irq(dev->dev, irq_dec, cedrus_irq,
cedrus_bh, 0, dev_name(dev->dev),
dev);
if (ret) {
v4l2_err(&dev->v4l2_dev, "Failed to request IRQ\n");
return ret;
}
/*
* The VPU is only able to handle bus addresses so we have to subtract
* the RAM offset to the physcal addresses.
*
* This information will eventually be obtained from device-tree.
*/
#ifdef PHYS_PFN_OFFSET
dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET;
#endif
ret = of_reserved_mem_device_init(dev->dev);
if (ret && ret != -ENODEV) {
v4l2_err(&dev->v4l2_dev, "Failed to reserve memory\n");
return ret;
}
ret = sunxi_sram_claim(dev->dev);
if (ret) {
v4l2_err(&dev->v4l2_dev, "Failed to claim SRAM\n");
goto err_mem;
}
dev->ahb_clk = devm_clk_get(dev->dev, "ahb");
if (IS_ERR(dev->ahb_clk)) {
v4l2_err(&dev->v4l2_dev, "Failed to get AHB clock\n");
ret = PTR_ERR(dev->ahb_clk);
goto err_sram;
}
dev->mod_clk = devm_clk_get(dev->dev, "mod");
if (IS_ERR(dev->mod_clk)) {
v4l2_err(&dev->v4l2_dev, "Failed to get MOD clock\n");
ret = PTR_ERR(dev->mod_clk);
goto err_sram;
}
dev->ram_clk = devm_clk_get(dev->dev, "ram");
if (IS_ERR(dev->ram_clk)) {
v4l2_err(&dev->v4l2_dev, "Failed to get RAM clock\n");
ret = PTR_ERR(dev->ram_clk);
goto err_sram;
}
dev->rstc = devm_reset_control_get(dev->dev, NULL);
if (IS_ERR(dev->rstc)) {
v4l2_err(&dev->v4l2_dev, "Failed to get reset control\n");
ret = PTR_ERR(dev->rstc);
goto err_sram;
}
res = platform_get_resource(dev->pdev, IORESOURCE_MEM, 0);
dev->base = devm_ioremap_resource(dev->dev, res);
if (!dev->base) {
v4l2_err(&dev->v4l2_dev, "Failed to map registers\n");
ret = -ENOMEM;
goto err_sram;
}
ret = clk_set_rate(dev->mod_clk, CEDRUS_CLOCK_RATE_DEFAULT);
if (ret) {
v4l2_err(&dev->v4l2_dev, "Failed to set clock rate\n");
goto err_sram;
}
ret = clk_prepare_enable(dev->ahb_clk);
if (ret) {
v4l2_err(&dev->v4l2_dev, "Failed to enable AHB clock\n");
goto err_sram;
}
ret = clk_prepare_enable(dev->mod_clk);
if (ret) {
v4l2_err(&dev->v4l2_dev, "Failed to enable MOD clock\n");
goto err_ahb_clk;
}
ret = clk_prepare_enable(dev->ram_clk);
if (ret) {
v4l2_err(&dev->v4l2_dev, "Failed to enable RAM clock\n");
goto err_mod_clk;
}
ret = reset_control_reset(dev->rstc);
if (ret) {
v4l2_err(&dev->v4l2_dev, "Failed to apply reset\n");
goto err_ram_clk;
}
return 0;
err_ram_clk:
clk_disable_unprepare(dev->ram_clk);
err_mod_clk:
clk_disable_unprepare(dev->mod_clk);
err_ahb_clk:
clk_disable_unprepare(dev->ahb_clk);
err_sram:
sunxi_sram_release(dev->dev);
err_mem:
of_reserved_mem_device_release(dev->dev);
return ret;
}
void cedrus_hw_remove(struct cedrus_dev *dev)
{
reset_control_assert(dev->rstc);
clk_disable_unprepare(dev->ram_clk);
clk_disable_unprepare(dev->mod_clk);
clk_disable_unprepare(dev->ahb_clk);
sunxi_sram_release(dev->dev);
of_reserved_mem_device_release(dev->dev);
}
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Cedrus VPU driver
*
* Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
* Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
* Copyright (C) 2018 Bootlin
*
* Based on the vim2m driver, that is:
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* Pawel Osciak, <pawel@osciak.com>
* Marek Szyprowski, <m.szyprowski@samsung.com>
*/
#ifndef _CEDRUS_HW_H_
#define _CEDRUS_HW_H_
#define CEDRUS_CLOCK_RATE_DEFAULT 320000000
int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec);
void cedrus_engine_disable(struct cedrus_dev *dev);
void cedrus_dst_format_set(struct cedrus_dev *dev,
struct v4l2_pix_format *fmt);
int cedrus_hw_probe(struct cedrus_dev *dev);
void cedrus_hw_remove(struct cedrus_dev *dev);
#endif
// SPDX-License-Identifier: GPL-2.0
/*
* Cedrus VPU driver
*
* Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
* Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
* Copyright (C) 2018 Bootlin
*/
#include <media/videobuf2-dma-contig.h>
#include "cedrus.h"
#include "cedrus_hw.h"
#include "cedrus_regs.h"
/* Default MPEG-2 quantization coefficients, from the specification. */
static const u8 intra_quantization_matrix_default[64] = {
8, 16, 16, 19, 16, 19, 22, 22,
22, 22, 22, 22, 26, 24, 26, 27,
27, 27, 26, 26, 26, 26, 27, 27,
27, 29, 29, 29, 34, 34, 34, 29,
29, 29, 27, 27, 29, 29, 32, 32,
34, 34, 37, 38, 37, 35, 35, 34,
35, 38, 38, 40, 40, 40, 48, 48,
46, 46, 56, 56, 58, 69, 69, 83
};
static const u8 non_intra_quantization_matrix_default[64] = {
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16
};
static enum cedrus_irq_status cedrus_mpeg2_irq_status(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
u32 reg;
reg = cedrus_read(dev, VE_DEC_MPEG_STATUS);
reg &= VE_DEC_MPEG_STATUS_CHECK_MASK;
if (!reg)
return CEDRUS_IRQ_NONE;
if (reg & VE_DEC_MPEG_STATUS_CHECK_ERROR ||
!(reg & VE_DEC_MPEG_STATUS_SUCCESS))
return CEDRUS_IRQ_ERROR;
return CEDRUS_IRQ_OK;
}
static void cedrus_mpeg2_irq_clear(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
cedrus_write(dev, VE_DEC_MPEG_STATUS, VE_DEC_MPEG_STATUS_CHECK_MASK);
}
static void cedrus_mpeg2_irq_disable(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
u32 reg = cedrus_read(dev, VE_DEC_MPEG_CTRL);
reg &= ~VE_DEC_MPEG_CTRL_IRQ_MASK;
cedrus_write(dev, VE_DEC_MPEG_CTRL, reg);
}
static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
{
const struct v4l2_ctrl_mpeg2_slice_params *slice_params;
const struct v4l2_mpeg2_sequence *sequence;
const struct v4l2_mpeg2_picture *picture;
const struct v4l2_ctrl_mpeg2_quantization *quantization;
dma_addr_t src_buf_addr, dst_luma_addr, dst_chroma_addr;
dma_addr_t fwd_luma_addr, fwd_chroma_addr;
dma_addr_t bwd_luma_addr, bwd_chroma_addr;
struct cedrus_dev *dev = ctx->dev;
const u8 *matrix;
unsigned int i;
u32 reg;
slice_params = run->mpeg2.slice_params;
sequence = &slice_params->sequence;
picture = &slice_params->picture;
quantization = run->mpeg2.quantization;
/* Activate MPEG engine. */
cedrus_engine_enable(dev, CEDRUS_CODEC_MPEG2);
/* Set intra quantization matrix. */
if (quantization && quantization->load_intra_quantiser_matrix)
matrix = quantization->intra_quantiser_matrix;
else
matrix = intra_quantization_matrix_default;
for (i = 0; i < 64; i++) {
reg = VE_DEC_MPEG_IQMINPUT_WEIGHT(i, matrix[i]);
reg |= VE_DEC_MPEG_IQMINPUT_FLAG_INTRA;
cedrus_write(dev, VE_DEC_MPEG_IQMINPUT, reg);
}
/* Set non-intra quantization matrix. */
if (quantization && quantization->load_non_intra_quantiser_matrix)
matrix = quantization->non_intra_quantiser_matrix;
else
matrix = non_intra_quantization_matrix_default;
for (i = 0; i < 64; i++) {
reg = VE_DEC_MPEG_IQMINPUT_WEIGHT(i, matrix[i]);
reg |= VE_DEC_MPEG_IQMINPUT_FLAG_NON_INTRA;
cedrus_write(dev, VE_DEC_MPEG_IQMINPUT, reg);
}
/* Set MPEG picture header. */
reg = VE_DEC_MPEG_MP12HDR_SLICE_TYPE(picture->picture_coding_type);
reg |= VE_DEC_MPEG_MP12HDR_F_CODE(0, 0, picture->f_code[0][0]);
reg |= VE_DEC_MPEG_MP12HDR_F_CODE(0, 1, picture->f_code[0][1]);
reg |= VE_DEC_MPEG_MP12HDR_F_CODE(1, 0, picture->f_code[1][0]);
reg |= VE_DEC_MPEG_MP12HDR_F_CODE(1, 1, picture->f_code[1][1]);
reg |= VE_DEC_MPEG_MP12HDR_INTRA_DC_PRECISION(picture->intra_dc_precision);
reg |= VE_DEC_MPEG_MP12HDR_INTRA_PICTURE_STRUCTURE(picture->picture_structure);
reg |= VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(picture->top_field_first);
reg |= VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(picture->frame_pred_frame_dct);
reg |= VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(picture->concealment_motion_vectors);
reg |= VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(picture->q_scale_type);
reg |= VE_DEC_MPEG_MP12HDR_INTRA_VLC_FORMAT(picture->intra_vlc_format);
reg |= VE_DEC_MPEG_MP12HDR_ALTERNATE_SCAN(picture->alternate_scan);
reg |= VE_DEC_MPEG_MP12HDR_FULL_PEL_FORWARD_VECTOR(0);
reg |= VE_DEC_MPEG_MP12HDR_FULL_PEL_BACKWARD_VECTOR(0);
cedrus_write(dev, VE_DEC_MPEG_MP12HDR, reg);
/* Set frame dimensions. */
reg = VE_DEC_MPEG_PICCODEDSIZE_WIDTH(sequence->horizontal_size);
reg |= VE_DEC_MPEG_PICCODEDSIZE_HEIGHT(sequence->vertical_size);
cedrus_write(dev, VE_DEC_MPEG_PICCODEDSIZE, reg);
reg = VE_DEC_MPEG_PICBOUNDSIZE_WIDTH(ctx->src_fmt.width);
reg |= VE_DEC_MPEG_PICBOUNDSIZE_HEIGHT(ctx->src_fmt.height);
cedrus_write(dev, VE_DEC_MPEG_PICBOUNDSIZE, reg);
/* Forward and backward prediction reference buffers. */
fwd_luma_addr = cedrus_dst_buf_addr(ctx,
slice_params->forward_ref_index,
0);
fwd_chroma_addr = cedrus_dst_buf_addr(ctx,
slice_params->forward_ref_index,
1);
cedrus_write(dev, VE_DEC_MPEG_FWD_REF_LUMA_ADDR, fwd_luma_addr);
cedrus_write(dev, VE_DEC_MPEG_FWD_REF_CHROMA_ADDR, fwd_chroma_addr);
bwd_luma_addr = cedrus_dst_buf_addr(ctx,
slice_params->backward_ref_index,
0);
bwd_chroma_addr = cedrus_dst_buf_addr(ctx,
slice_params->backward_ref_index,
1);
cedrus_write(dev, VE_DEC_MPEG_BWD_REF_LUMA_ADDR, bwd_luma_addr);
cedrus_write(dev, VE_DEC_MPEG_BWD_REF_CHROMA_ADDR, bwd_chroma_addr);
/* Destination luma and chroma buffers. */
dst_luma_addr = cedrus_dst_buf_addr(ctx, run->dst->vb2_buf.index, 0);
dst_chroma_addr = cedrus_dst_buf_addr(ctx, run->dst->vb2_buf.index, 1);
cedrus_write(dev, VE_DEC_MPEG_REC_LUMA, dst_luma_addr);
cedrus_write(dev, VE_DEC_MPEG_REC_CHROMA, dst_chroma_addr);
/* Source offset and length in bits. */
cedrus_write(dev, VE_DEC_MPEG_VLD_OFFSET,
slice_params->data_bit_offset);
reg = slice_params->bit_size - slice_params->data_bit_offset;
cedrus_write(dev, VE_DEC_MPEG_VLD_LEN, reg);
/* Source beginning and end addresses. */
src_buf_addr = vb2_dma_contig_plane_dma_addr(&run->src->vb2_buf, 0);
reg = VE_DEC_MPEG_VLD_ADDR_BASE(src_buf_addr);
reg |= VE_DEC_MPEG_VLD_ADDR_VALID_PIC_DATA;
reg |= VE_DEC_MPEG_VLD_ADDR_LAST_PIC_DATA;
reg |= VE_DEC_MPEG_VLD_ADDR_FIRST_PIC_DATA;
cedrus_write(dev, VE_DEC_MPEG_VLD_ADDR, reg);
reg = src_buf_addr + DIV_ROUND_UP(slice_params->bit_size, 8);
cedrus_write(dev, VE_DEC_MPEG_VLD_END_ADDR, reg);
/* Macroblock address: start at the beginning. */
reg = VE_DEC_MPEG_MBADDR_Y(0) | VE_DEC_MPEG_MBADDR_X(0);
cedrus_write(dev, VE_DEC_MPEG_MBADDR, reg);
/* Clear previous errors. */
cedrus_write(dev, VE_DEC_MPEG_ERROR, 0);
/* Clear correct macroblocks register. */
cedrus_write(dev, VE_DEC_MPEG_CRTMBADDR, 0);
/* Enable appropriate interruptions and components. */
reg = VE_DEC_MPEG_CTRL_IRQ_MASK | VE_DEC_MPEG_CTRL_MC_NO_WRITEBACK |
VE_DEC_MPEG_CTRL_MC_CACHE_EN;
cedrus_write(dev, VE_DEC_MPEG_CTRL, reg);
}
static void cedrus_mpeg2_trigger(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
u32 reg;
/* Trigger MPEG engine. */
reg = VE_DEC_MPEG_TRIGGER_HW_MPEG_VLD | VE_DEC_MPEG_TRIGGER_MPEG2 |
VE_DEC_MPEG_TRIGGER_MB_BOUNDARY;
cedrus_write(dev, VE_DEC_MPEG_TRIGGER, reg);
}
struct cedrus_dec_ops cedrus_dec_ops_mpeg2 = {
.irq_clear = cedrus_mpeg2_irq_clear,
.irq_disable = cedrus_mpeg2_irq_disable,
.irq_status = cedrus_mpeg2_irq_status,
.setup = cedrus_mpeg2_setup,
.trigger = cedrus_mpeg2_trigger,
};
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Cedrus VPU driver
*
* Copyright (c) 2013-2016 Jens Kuske <jenskuske@gmail.com>
* Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
* Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
*/
#ifndef _CEDRUS_REGS_H_
#define _CEDRUS_REGS_H_
/*
* Common acronyms and contractions used in register descriptions:
* * VLD : Variable-Length Decoder
* * IQ: Inverse Quantization
* * IDCT: Inverse Discrete Cosine Transform
* * MC: Motion Compensation
* * STCD: Start Code Detect
* * SDRT: Scale Down and Rotate
*/
#define VE_ENGINE_DEC_MPEG 0x100
#define VE_ENGINE_DEC_H264 0x200
#define VE_MODE 0x00
#define VE_MODE_REC_WR_MODE_2MB (0x01 << 20)
#define VE_MODE_REC_WR_MODE_1MB (0x00 << 20)
#define VE_MODE_DDR_MODE_BW_128 (0x03 << 16)
#define VE_MODE_DDR_MODE_BW_256 (0x02 << 16)
#define VE_MODE_DISABLED (0x07 << 0)
#define VE_MODE_DEC_H265 (0x04 << 0)
#define VE_MODE_DEC_H264 (0x01 << 0)
#define VE_MODE_DEC_MPEG (0x00 << 0)
#define VE_PRIMARY_CHROMA_BUF_LEN 0xc4
#define VE_PRIMARY_FB_LINE_STRIDE 0xc8
#define VE_PRIMARY_FB_LINE_STRIDE_CHROMA(s) (((s) << 16) & GENMASK(31, 16))
#define VE_PRIMARY_FB_LINE_STRIDE_LUMA(s) (((s) << 0) & GENMASK(15, 0))
#define VE_CHROMA_BUF_LEN 0xe8
#define VE_SECONDARY_OUT_FMT_TILED_32_NV12 (0x00 << 30)
#define VE_SECONDARY_OUT_FMT_EXT (0x01 << 30)
#define VE_SECONDARY_OUT_FMT_YU12 (0x02 << 30)
#define VE_SECONDARY_OUT_FMT_YV12 (0x03 << 30)
#define VE_CHROMA_BUF_LEN_SDRT(l) ((l) & GENMASK(27, 0))
#define VE_PRIMARY_OUT_FMT 0xec
#define VE_PRIMARY_OUT_FMT_TILED_32_NV12 (0x00 << 4)
#define VE_PRIMARY_OUT_FMT_TILED_128_NV12 (0x01 << 4)
#define VE_PRIMARY_OUT_FMT_YU12 (0x02 << 4)
#define VE_PRIMARY_OUT_FMT_YV12 (0x03 << 4)
#define VE_PRIMARY_OUT_FMT_NV12 (0x04 << 4)
#define VE_PRIMARY_OUT_FMT_NV21 (0x05 << 4)
#define VE_SECONDARY_OUT_FMT_EXT_TILED_32_NV12 (0x00 << 0)
#define VE_SECONDARY_OUT_FMT_EXT_TILED_128_NV12 (0x01 << 0)
#define VE_SECONDARY_OUT_FMT_EXT_YU12 (0x02 << 0)
#define VE_SECONDARY_OUT_FMT_EXT_YV12 (0x03 << 0)
#define VE_SECONDARY_OUT_FMT_EXT_NV12 (0x04 << 0)
#define VE_SECONDARY_OUT_FMT_EXT_NV21 (0x05 << 0)
#define VE_VERSION 0xf0
#define VE_VERSION_SHIFT 16
#define VE_DEC_MPEG_MP12HDR (VE_ENGINE_DEC_MPEG + 0x00)
#define VE_DEC_MPEG_MP12HDR_SLICE_TYPE(t) (((t) << 28) & GENMASK(30, 28))
#define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y) (24 - 4 * (y) - 8 * (x))
#define VE_DEC_MPEG_MP12HDR_F_CODE(__x, __y, __v) \
(((__v) & GENMASK(3, 0)) << VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(__x, __y))
#define VE_DEC_MPEG_MP12HDR_INTRA_DC_PRECISION(p) \
(((p) << 10) & GENMASK(11, 10))
#define VE_DEC_MPEG_MP12HDR_INTRA_PICTURE_STRUCTURE(s) \
(((s) << 8) & GENMASK(9, 8))
#define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \
((v) ? BIT(7) : 0)
#define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \
((v) ? BIT(6) : 0)
#define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \
((v) ? BIT(5) : 0)
#define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \
((v) ? BIT(4) : 0)
#define VE_DEC_MPEG_MP12HDR_INTRA_VLC_FORMAT(v) \
((v) ? BIT(3) : 0)
#define VE_DEC_MPEG_MP12HDR_ALTERNATE_SCAN(v) \
((v) ? BIT(2) : 0)
#define VE_DEC_MPEG_MP12HDR_FULL_PEL_FORWARD_VECTOR(v) \
((v) ? BIT(1) : 0)
#define VE_DEC_MPEG_MP12HDR_FULL_PEL_BACKWARD_VECTOR(v) \
((v) ? BIT(0) : 0)
#define VE_DEC_MPEG_PICCODEDSIZE (VE_ENGINE_DEC_MPEG + 0x08)
#define VE_DEC_MPEG_PICCODEDSIZE_WIDTH(w) \
((DIV_ROUND_UP((w), 16) << 8) & GENMASK(15, 8))
#define VE_DEC_MPEG_PICCODEDSIZE_HEIGHT(h) \
((DIV_ROUND_UP((h), 16) << 0) & GENMASK(7, 0))
#define VE_DEC_MPEG_PICBOUNDSIZE (VE_ENGINE_DEC_MPEG + 0x0c)
#define VE_DEC_MPEG_PICBOUNDSIZE_WIDTH(w) (((w) << 16) & GENMASK(27, 16))
#define VE_DEC_MPEG_PICBOUNDSIZE_HEIGHT(h) (((h) << 0) & GENMASK(11, 0))
#define VE_DEC_MPEG_MBADDR (VE_ENGINE_DEC_MPEG + 0x10)
#define VE_DEC_MPEG_MBADDR_X(w) (((w) << 8) & GENMASK(15, 8))
#define VE_DEC_MPEG_MBADDR_Y(h) (((h) << 0) & GENMASK(0, 7))
#define VE_DEC_MPEG_CTRL (VE_ENGINE_DEC_MPEG + 0x14)
#define VE_DEC_MPEG_CTRL_MC_CACHE_EN BIT(31)
#define VE_DEC_MPEG_CTRL_SW_VLD BIT(27)
#define VE_DEC_MPEG_CTRL_SW_IQ_IS BIT(17)
#define VE_DEC_MPEG_CTRL_QP_AC_DC_OUT_EN BIT(14)
#define VE_DEC_MPEG_CTRL_ROTATE_SCALE_OUT_EN BIT(8)
#define VE_DEC_MPEG_CTRL_MC_NO_WRITEBACK BIT(7)
#define VE_DEC_MPEG_CTRL_ROTATE_IRQ_EN BIT(6)
#define VE_DEC_MPEG_CTRL_VLD_DATA_REQ_IRQ_EN BIT(5)
#define VE_DEC_MPEG_CTRL_ERROR_IRQ_EN BIT(4)
#define VE_DEC_MPEG_CTRL_FINISH_IRQ_EN BIT(3)
#define VE_DEC_MPEG_CTRL_IRQ_MASK \
(VE_DEC_MPEG_CTRL_FINISH_IRQ_EN | VE_DEC_MPEG_CTRL_ERROR_IRQ_EN | \
VE_DEC_MPEG_CTRL_VLD_DATA_REQ_IRQ_EN)
#define VE_DEC_MPEG_TRIGGER (VE_ENGINE_DEC_MPEG + 0x18)
#define VE_DEC_MPEG_TRIGGER_MB_BOUNDARY BIT(31)
#define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_420 (0x00 << 27)
#define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_411 (0x01 << 27)
#define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_422 (0x02 << 27)
#define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_444 (0x03 << 27)
#define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_422T (0x04 << 27)
#define VE_DEC_MPEG_TRIGGER_MPEG1 (0x01 << 24)
#define VE_DEC_MPEG_TRIGGER_MPEG2 (0x02 << 24)
#define VE_DEC_MPEG_TRIGGER_JPEG (0x03 << 24)
#define VE_DEC_MPEG_TRIGGER_MPEG4 (0x04 << 24)
#define VE_DEC_MPEG_TRIGGER_VP62 (0x05 << 24)
#define VE_DEC_MPEG_TRIGGER_VP62_AC_GET_BITS BIT(7)
#define VE_DEC_MPEG_TRIGGER_STCD_VC1 (0x02 << 4)
#define VE_DEC_MPEG_TRIGGER_STCD_MPEG2 (0x01 << 4)
#define VE_DEC_MPEG_TRIGGER_STCD_AVC (0x00 << 4)
#define VE_DEC_MPEG_TRIGGER_HW_MPEG_VLD (0x0f << 0)
#define VE_DEC_MPEG_TRIGGER_HW_JPEG_VLD (0x0e << 0)
#define VE_DEC_MPEG_TRIGGER_HW_MB (0x0d << 0)
#define VE_DEC_MPEG_TRIGGER_HW_ROTATE (0x0c << 0)
#define VE_DEC_MPEG_TRIGGER_HW_VP6_VLD (0x0b << 0)
#define VE_DEC_MPEG_TRIGGER_HW_MAF (0x0a << 0)
#define VE_DEC_MPEG_TRIGGER_HW_STCD_END (0x09 << 0)
#define VE_DEC_MPEG_TRIGGER_HW_STCD_BEGIN (0x08 << 0)
#define VE_DEC_MPEG_TRIGGER_SW_MC (0x07 << 0)
#define VE_DEC_MPEG_TRIGGER_SW_IQ (0x06 << 0)
#define VE_DEC_MPEG_TRIGGER_SW_IDCT (0x05 << 0)
#define VE_DEC_MPEG_TRIGGER_SW_SCALE (0x04 << 0)
#define VE_DEC_MPEG_TRIGGER_SW_VP6 (0x03 << 0)
#define VE_DEC_MPEG_TRIGGER_SW_VP62_AC_GET_BITS (0x02 << 0)
#define VE_DEC_MPEG_STATUS (VE_ENGINE_DEC_MPEG + 0x1c)
#define VE_DEC_MPEG_STATUS_START_DETECT_BUSY BIT(27)
#define VE_DEC_MPEG_STATUS_VP6_BIT BIT(26)
#define VE_DEC_MPEG_STATUS_VP6_BIT_BUSY BIT(25)
#define VE_DEC_MPEG_STATUS_MAF_BUSY BIT(23)
#define VE_DEC_MPEG_STATUS_VP6_MVP_BUSY BIT(22)
#define VE_DEC_MPEG_STATUS_JPEG_BIT_END BIT(21)
#define VE_DEC_MPEG_STATUS_JPEG_RESTART_ERROR BIT(20)
#define VE_DEC_MPEG_STATUS_JPEG_MARKER BIT(19)
#define VE_DEC_MPEG_STATUS_ROTATE_BUSY BIT(18)
#define VE_DEC_MPEG_STATUS_DEBLOCKING_BUSY BIT(17)
#define VE_DEC_MPEG_STATUS_SCALE_DOWN_BUSY BIT(16)
#define VE_DEC_MPEG_STATUS_IQIS_BUF_EMPTY BIT(15)
#define VE_DEC_MPEG_STATUS_IDCT_BUF_EMPTY BIT(14)
#define VE_DEC_MPEG_STATUS_VE_BUSY BIT(13)
#define VE_DEC_MPEG_STATUS_MC_BUSY BIT(12)
#define VE_DEC_MPEG_STATUS_IDCT_BUSY BIT(11)
#define VE_DEC_MPEG_STATUS_IQIS_BUSY BIT(10)
#define VE_DEC_MPEG_STATUS_DCAC_BUSY BIT(9)
#define VE_DEC_MPEG_STATUS_VLD_BUSY BIT(8)
#define VE_DEC_MPEG_STATUS_ROTATE_SUCCESS BIT(3)
#define VE_DEC_MPEG_STATUS_VLD_DATA_REQ BIT(2)
#define VE_DEC_MPEG_STATUS_ERROR BIT(1)
#define VE_DEC_MPEG_STATUS_SUCCESS BIT(0)
#define VE_DEC_MPEG_STATUS_CHECK_MASK \
(VE_DEC_MPEG_STATUS_SUCCESS | VE_DEC_MPEG_STATUS_ERROR | \
VE_DEC_MPEG_STATUS_VLD_DATA_REQ)
#define VE_DEC_MPEG_STATUS_CHECK_ERROR \
(VE_DEC_MPEG_STATUS_ERROR | VE_DEC_MPEG_STATUS_VLD_DATA_REQ)
#define VE_DEC_MPEG_VLD_ADDR (VE_ENGINE_DEC_MPEG + 0x28)
#define VE_DEC_MPEG_VLD_ADDR_FIRST_PIC_DATA BIT(30)
#define VE_DEC_MPEG_VLD_ADDR_LAST_PIC_DATA BIT(29)
#define VE_DEC_MPEG_VLD_ADDR_VALID_PIC_DATA BIT(28)
#define VE_DEC_MPEG_VLD_ADDR_BASE(a) \
({ \
u32 _tmp = (a); \
u32 _lo = _tmp & GENMASK(27, 4); \
u32 _hi = (_tmp >> 28) & GENMASK(3, 0); \
(_lo | _hi); \
})
#define VE_DEC_MPEG_VLD_OFFSET (VE_ENGINE_DEC_MPEG + 0x2c)
#define VE_DEC_MPEG_VLD_LEN (VE_ENGINE_DEC_MPEG + 0x30)
#define VE_DEC_MPEG_VLD_END_ADDR (VE_ENGINE_DEC_MPEG + 0x34)
#define VE_DEC_MPEG_REC_LUMA (VE_ENGINE_DEC_MPEG + 0x48)
#define VE_DEC_MPEG_REC_CHROMA (VE_ENGINE_DEC_MPEG + 0x4c)
#define VE_DEC_MPEG_FWD_REF_LUMA_ADDR (VE_ENGINE_DEC_MPEG + 0x50)
#define VE_DEC_MPEG_FWD_REF_CHROMA_ADDR (VE_ENGINE_DEC_MPEG + 0x54)
#define VE_DEC_MPEG_BWD_REF_LUMA_ADDR (VE_ENGINE_DEC_MPEG + 0x58)
#define VE_DEC_MPEG_BWD_REF_CHROMA_ADDR (VE_ENGINE_DEC_MPEG + 0x5c)
#define VE_DEC_MPEG_IQMINPUT (VE_ENGINE_DEC_MPEG + 0x80)
#define VE_DEC_MPEG_IQMINPUT_FLAG_INTRA (0x01 << 14)
#define VE_DEC_MPEG_IQMINPUT_FLAG_NON_INTRA (0x00 << 14)
#define VE_DEC_MPEG_IQMINPUT_WEIGHT(i, v) \
(((v) & GENMASK(7, 0)) | (((i) << 8) & GENMASK(13, 8)))
#define VE_DEC_MPEG_ERROR (VE_ENGINE_DEC_MPEG + 0xc4)
#define VE_DEC_MPEG_CRTMBADDR (VE_ENGINE_DEC_MPEG + 0xc8)
#define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc)
#define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0)
#endif
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Cedrus VPU driver
*
* Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
* Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
* Copyright (C) 2018 Bootlin
*
* Based on the vim2m driver, that is:
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* Pawel Osciak, <pawel@osciak.com>
* Marek Szyprowski, <m.szyprowski@samsung.com>
*/
#ifndef _CEDRUS_VIDEO_H_
#define _CEDRUS_VIDEO_H_
struct cedrus_format {
u32 pixelformat;
u32 directions;
unsigned int capabilities;
};
extern const struct v4l2_ioctl_ops cedrus_ioctl_ops;
int cedrus_queue_init(void *priv, struct vb2_queue *src_vq,
struct vb2_queue *dst_vq);
#endif
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment