Commit 5110e655 authored by Harsh Jain's avatar Harsh Jain Committed by Herbert Xu

crypto: chelsio -Split Hash requests for large scatter gather list

Send multiple WRs to H/W when No. of entries received in scatter list
cannot be sent in single request.
Signed-off-by: default avatarHarsh Jain <harsh@chelsio.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 7ffb9118
This diff is collapsed.
......@@ -222,8 +222,10 @@
#define MIN_GCM_SG 1 /* IV */
#define MIN_DIGEST_SG 1 /*Partial Buffer*/
#define MIN_CCM_SG 2 /*IV+B0*/
#define SPACE_LEFT(len) \
((SGE_MAX_WR_LEN - WR_MIN_LEN - (len)))
#define CIP_SPACE_LEFT(len) \
((SGE_MAX_WR_LEN - CIP_WR_MIN_LEN - (len)))
#define HASH_SPACE_LEFT(len) \
((SGE_MAX_WR_LEN - HASH_WR_MIN_LEN - (len)))
struct algo_param {
unsigned int auth_mode;
......@@ -232,12 +234,14 @@ struct algo_param {
};
struct hash_wr_param {
struct algo_param alg_prm;
unsigned int opad_needed;
unsigned int more;
unsigned int last;
struct algo_param alg_prm;
unsigned int kctx_len;
unsigned int sg_len;
unsigned int bfr_len;
unsigned int hash_size;
u64 scmd1;
};
......
......@@ -54,10 +54,14 @@
#define MAC_ERROR_BIT 0
#define CHK_MAC_ERR_BIT(x) (((x) >> MAC_ERROR_BIT) & 1)
#define MAX_SALT 4
#define WR_MIN_LEN (sizeof(struct chcr_wr) + \
#define CIP_WR_MIN_LEN (sizeof(struct chcr_wr) + \
sizeof(struct cpl_rx_phys_dsgl) + \
sizeof(struct ulptx_sgl))
#define HASH_WR_MIN_LEN (sizeof(struct chcr_wr) + \
DUMMY_BYTES + \
sizeof(struct ulptx_sgl))
#define padap(dev) pci_get_drvdata(dev->u_ctx->lldi.pdev)
struct uld_ctx;
......
......@@ -258,21 +258,32 @@ struct chcr_context {
struct __crypto_ctx crypto_ctx[0];
};
struct chcr_ahash_req_ctx {
struct chcr_hctx_per_wr {
struct scatterlist *srcsg;
struct sk_buff *skb;
dma_addr_t dma_addr;
u32 dma_len;
unsigned int src_ofst;
unsigned int processed;
u32 result;
u8 bfr1[CHCR_HASH_MAX_BLOCK_SIZE_128];
u8 bfr2[CHCR_HASH_MAX_BLOCK_SIZE_128];
u8 is_sg_map;
u8 imm;
/*Final callback called. Driver cannot rely on nbytes to decide
* final call
*/
u8 isfinal;
};
struct chcr_ahash_req_ctx {
struct chcr_hctx_per_wr hctx_wr;
u8 *reqbfr;
u8 *skbfr;
dma_addr_t dma_addr;
u32 dma_len;
/* SKB which is being sent to the hardware for processing */
u64 data_len; /* Data len till time */
u8 reqlen;
u8 imm;
u8 is_sg_map;
u8 partial_hash[CHCR_HASH_MAX_DIGEST_SIZE];
u64 data_len; /* Data len till time */
/* SKB which is being sent to the hardware for processing */
struct sk_buff *skb;
u8 bfr1[CHCR_HASH_MAX_BLOCK_SIZE_128];
u8 bfr2[CHCR_HASH_MAX_BLOCK_SIZE_128];
};
struct chcr_blkcipher_req_ctx {
......@@ -329,4 +340,5 @@ void chcr_add_hash_src_ent(struct ahash_request *req, struct ulptx_sgl *ulptx,
struct hash_wr_param *param);
int chcr_hash_dma_map(struct device *dev, struct ahash_request *req);
void chcr_hash_dma_unmap(struct device *dev, struct ahash_request *req);
static int chcr_ahash_continue(struct ahash_request *req);
#endif /* __CHCR_CRYPTO_H__ */
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