Commit 51302162 authored by Barry Song's avatar Barry Song Committed by Barry Song

PINCTRL: SiRF: add GPIO and GPIO irq support in CSR SiRFprimaII

In SiRFprimaII, Each GPIO pin can be configured as input or output
independently. If a GPIO is configured as input, it can also be
enabled as an interrupt source (either edge or level triggered).

These pins must be either MUXed as GPIO or other function pads.
Signed-off-by: default avatarYuping Luo <yuping.luo@csr.com>
Signed-off-by: default avatarBarry Song <Baohua.Song@csr.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent ca24a145
...@@ -389,6 +389,7 @@ config ARCH_PRIMA2 ...@@ -389,6 +389,7 @@ config ARCH_PRIMA2
bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
select CPU_V7 select CPU_V7
select NO_IOPORT select NO_IOPORT
select ARCH_WANT_OPTIONAL_GPIOLIB
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP select CLKDEV_LOOKUP
select GENERIC_IRQ_CHIP select GENERIC_IRQ_CHIP
......
#ifndef __MACH_GPIO_H
#define __MACH_GPIO_H
/* Pull up/down values */
enum sirfsoc_gpio_pull {
SIRFSOC_GPIO_PULL_NONE,
SIRFSOC_GPIO_PULL_UP,
SIRFSOC_GPIO_PULL_DOWN,
};
void sirfsoc_gpio_set_pull(unsigned gpio, unsigned mode);
#endif
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#define SIRFSOC_INTENAL_IRQ_START 0 #define SIRFSOC_INTENAL_IRQ_START 0
#define SIRFSOC_INTENAL_IRQ_END 59 #define SIRFSOC_INTENAL_IRQ_END 59
#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1)
#define NR_IRQS 220 #define NR_IRQS 220
#endif #endif
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