Commit 51a15881 authored by Jordan Niethe's avatar Jordan Niethe Committed by Michael Ellerman

powerpc: Update documentation of ISA versions for Power10

Update the CPU to ISA Version Mapping document to include Power10 and
ISA v3.1.
Signed-off-by: default avatarJordan Niethe <jniethe5@gmail.com>
[mpe: Make sure ISA reference is unique]
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200827040556.1783-1-jniethe5@gmail.com
parent 0fb4871b
...@@ -7,6 +7,7 @@ Mapping of some CPU versions to relevant ISA versions. ...@@ -7,6 +7,7 @@ Mapping of some CPU versions to relevant ISA versions.
========= ==================================================================== ========= ====================================================================
CPU Architecture version CPU Architecture version
========= ==================================================================== ========= ====================================================================
Power10 Power ISA v3.1
Power9 Power ISA v3.0B Power9 Power ISA v3.0B
Power8 Power ISA v2.07 Power8 Power ISA v2.07
Power7 Power ISA v2.06 Power7 Power ISA v2.06
...@@ -32,6 +33,7 @@ Key Features ...@@ -32,6 +33,7 @@ Key Features
========== ================== ========== ==================
CPU VMX (aka. Altivec) CPU VMX (aka. Altivec)
========== ================== ========== ==================
Power10 Yes
Power9 Yes Power9 Yes
Power8 Yes Power8 Yes
Power7 Yes Power7 Yes
...@@ -47,6 +49,7 @@ PPC970 Yes ...@@ -47,6 +49,7 @@ PPC970 Yes
========== ==== ========== ====
CPU VSX CPU VSX
========== ==== ========== ====
Power10 Yes
Power9 Yes Power9 Yes
Power8 Yes Power8 Yes
Power7 Yes Power7 Yes
...@@ -62,6 +65,7 @@ PPC970 No ...@@ -62,6 +65,7 @@ PPC970 No
========== ==================================== ========== ====================================
CPU Transactional Memory CPU Transactional Memory
========== ==================================== ========== ====================================
Power10 No (* see Power ISA v3.1, "Appendix A. Notes on the Removal of Transactional Memory from the Architecture")
Power9 Yes (* see transactional_memory.txt) Power9 Yes (* see transactional_memory.txt)
Power8 Yes Power8 Yes
Power7 No Power7 No
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment