Commit 521e8bac authored by Stephane Eranian's avatar Stephane Eranian Committed by Ingo Molnar

perf/x86/intel/uncore: Update support for client uncore IMC PMU

This patch restructures the memory controller (IMC) uncore PMU support
for client SNB/IVB/HSW processors. The main change is that it can now
cope with more than one PCI device ID per processor model. There are
many flavors of memory controllers for each processor. They have
different PCI device ID, yet they behave the same w.r.t. the memory
controller PMU that we are interested in.

The patch now supports two distinct memory controllers for IVB
processors: one for mobile, one for desktop.
Signed-off-by: default avatarStephane Eranian <eranian@google.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20140917090616.GA11281@quad
Cc: ak@linux.intel.com
Cc: kan.liang@intel.com
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent b10fc1c3
...@@ -460,6 +460,10 @@ static const struct pci_device_id ivb_uncore_pci_ids[] = { ...@@ -460,6 +460,10 @@ static const struct pci_device_id ivb_uncore_pci_ids[] = {
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC), PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC),
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
}, },
{ /* IMC */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_E3_IMC),
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
},
{ /* end: all zeroes */ }, { /* end: all zeroes */ },
}; };
...@@ -486,34 +490,63 @@ static struct pci_driver hsw_uncore_pci_driver = { ...@@ -486,34 +490,63 @@ static struct pci_driver hsw_uncore_pci_driver = {
.id_table = hsw_uncore_pci_ids, .id_table = hsw_uncore_pci_ids,
}; };
int snb_uncore_pci_init(void) struct imc_uncore_pci_dev {
__u32 pci_id;
struct pci_driver *driver;
};
#define IMC_DEV(a, d) \
{ .pci_id = PCI_DEVICE_ID_INTEL_##a, .driver = (d) }
static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
IMC_DEV(SNB_IMC, &snb_uncore_pci_driver),
IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver), /* 3rd Gen Core processor */
IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */
IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core Processor */
{ /* end marker */ }
};
#define for_each_imc_pci_id(x, t) \
for (x = (t); (x)->pci_id; x++)
static struct pci_driver *imc_uncore_find_dev(void)
{ {
int ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_SNB_IMC); const struct imc_uncore_pci_dev *p;
if (ret) int ret;
return ret;
uncore_pci_uncores = snb_pci_uncores; for_each_imc_pci_id(p, desktop_imc_pci_ids) {
uncore_pci_driver = &snb_uncore_pci_driver; ret = snb_pci2phy_map_init(p->pci_id);
return 0; if (ret == 0)
return p->driver;
}
return NULL;
} }
int ivb_uncore_pci_init(void) static int imc_uncore_pci_init(void)
{ {
int ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_IVB_IMC); struct pci_driver *imc_drv = imc_uncore_find_dev();
if (ret)
return ret; if (!imc_drv)
return -ENODEV;
uncore_pci_uncores = snb_pci_uncores; uncore_pci_uncores = snb_pci_uncores;
uncore_pci_driver = &ivb_uncore_pci_driver; uncore_pci_driver = imc_drv;
return 0; return 0;
} }
int snb_uncore_pci_init(void)
{
return imc_uncore_pci_init();
}
int ivb_uncore_pci_init(void)
{
return imc_uncore_pci_init();
}
int hsw_uncore_pci_init(void) int hsw_uncore_pci_init(void)
{ {
int ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_HSW_IMC); return imc_uncore_pci_init();
if (ret)
return ret;
uncore_pci_uncores = snb_pci_uncores;
uncore_pci_driver = &hsw_uncore_pci_driver;
return 0;
} }
/* end of Sandy Bridge uncore support */ /* end of Sandy Bridge uncore support */
......
...@@ -2536,6 +2536,7 @@ ...@@ -2536,6 +2536,7 @@
#define PCI_DEVICE_ID_INTEL_EESSC 0x0008 #define PCI_DEVICE_ID_INTEL_EESSC 0x0008
#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100 #define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154 #define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
#define PCI_DEVICE_ID_INTEL_IVB_E3_IMC 0x0150
#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00 #define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
#define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320 #define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320
#define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321 #define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321
......
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