Commit 52a0f00b authored by Chandrakala Chavva's avatar Chandrakala Chavva Committed by Ralf Baechle

MIPS: Octeon: Disallow MSI-X interrupt and fall back to MSI interrupts.

MSI-X interrupts are not supported yet for Octeon, return error if
MSI-X interrupts are requested by driver so that the driver will fall
back to use MSI interrupts.
Signed-off-by: default avatarChandrakala Chavva <cchavva@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/1506/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
parent 1aa2b278
...@@ -140,6 +140,11 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) ...@@ -140,6 +140,11 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
return channel ? 15 : 14; return channel ? 15 : 14;
} }
#ifdef CONFIG_CPU_CAVIUM_OCTEON
/* MSI arch hook for OCTEON */
#define arch_setup_msi_irqs arch_setup_msi_irqs
#endif
extern int pci_probe_only; extern int pci_probe_only;
extern char * (*pcibios_plat_setup)(char *str); extern char * (*pcibios_plat_setup)(char *str);
......
...@@ -177,6 +177,34 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) ...@@ -177,6 +177,34 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
return 0; return 0;
} }
int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
struct msi_desc *entry;
int ret;
/*
* MSI-X is not supported.
*/
if (type == PCI_CAP_ID_MSIX)
return -EINVAL;
/*
* If an architecture wants to support multiple MSI, it needs to
* override arch_setup_msi_irqs()
*/
if (type == PCI_CAP_ID_MSI && nvec > 1)
return 1;
list_for_each_entry(entry, &dev->msi_list, list) {
ret = arch_setup_msi_irq(dev, entry);
if (ret < 0)
return ret;
if (ret > 0)
return -ENOSPC;
}
return 0;
}
/** /**
* Called when a device no longer needs its MSI interrupts. All * Called when a device no longer needs its MSI interrupts. All
......
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