clk: socfpga: remove clk_ops enable/disable methods

The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lkml.kernel.org/r/20200512181647.5071-2-dinguyen@kernel.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

clk: socfpga: remove clk_ops enable/disable methods
The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lkml.kernel.org/r/20200512181647.5071-2-dinguyen@kernel.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>
535d936f · Dinh Nguyen · Stephen Boyd · 762d961a · 535d936f · 535d936f
Commit 535d936f authored May 12, 2020 by Dinh Nguyen Committed by Stephen Boyd May 26, 2020
Showing with 0 additions and 6 deletions

drivers/clk/socfpga/clk-pll-a10.c drivers/clk/socfpga/clk-pll-a10.c +0 -2

drivers/clk/socfpga/clk-pll-s10.c drivers/clk/socfpga/clk-pll-s10.c +0 -2

drivers/clk/socfpga/clk-pll.c drivers/clk/socfpga/clk-pll.c +0 -2

No files found.
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
 	pll_clk->hw.hw.init = &init;

 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;

 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {

--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
 	pll_clk->hw.hw.init = &init;

 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;

 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {

--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
 	pll_clk->hw.hw.init = &init;

 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;

 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {