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Commit 53ef168a authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://ppc.bkbits.net/for-linus-ppc 

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents 9fa12b00 07d78b7f
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Showing with 814 additions and 808 deletions
arch/ppc/4xx_io/serial_sicc.c
View file @ 53ef168a
......@@ -763,7 +763,7 @@ static void siccuart_change_speed(struct SICC_info *info, struct termios *old_te
cflag = info->tty->termios->c_cflag;
#if DEBUG
#ifdef DEBUG
printk("siccuart_set_cflag(0x%x) called\n", cflag);
#endif
/* byte size and parity */
......@@ -1027,7 +1027,7 @@ static void siccuart_flush_buffer(struct tty_struct *tty)
struct SICC_info *info = tty->driver_data;
unsigned long flags;
#if DEBUG
#ifdef DEBUG
printk("siccuart_flush_buffer(%d) called\n", tty->index);
#endif
save_flags(flags); cli();
......@@ -1433,7 +1433,7 @@ static void siccuart_close(struct tty_struct *tty, struct file *filp)
state = info->state;
#if DEBUG
#ifdef DEBUG
//printk("siccuart_close() called\n");
#endif
......@@ -1544,7 +1544,7 @@ static void siccuart_wait_until_sent(struct tty_struct *tty, int timeout)
timeout = 2 * info->timeout;
expire = jiffies + timeout;
#if DEBUG
#ifdef DEBUG
printk("siccuart_wait_until_sent(%d), jiff=%lu, expire=%lu char_time=%lu...\n",
tty->index, jiffies,
expire, char_time);
......@@ -1831,7 +1831,7 @@ static int siccuart_console_read(struct console *co, const char *s, u_int count)
unsigned int status;
char *w;
int c;
#if DEBUG
#ifdef DEBUG
printk("siccuart_console_read() called\n");
#endif
......
arch/ppc/8260_io/uart.c
View file @ 53ef168a
......@@ -155,7 +155,7 @@ static unsigned long break_pressed; /* break, really ... */
static struct serial_state rs_table[] = {
/* UART CLK PORT IRQ FLAGS NUM */
{ 0, 0, PROFF_SMC1, SIU_INT_SMC1, 0, 0 }, /* SMC1 ttyS0 */
#if USE_SMC2
#ifdef USE_SMC2
{ 0, 0, PROFF_SMC2, SIU_INT_SMC2, 0, 1 }, /* SMC2 ttyS1 */
#endif
#ifndef CONFIG_SCC1_ENET
......@@ -2565,7 +2565,7 @@ static int __init rs_8xx_init(void)
io->iop_pdird |= 0x00400000;
io->iop_pdird &= ~0x00800000;
io->iop_psord &= ~0x00c00000;
#if USE_SMC2
#ifdef USE_SMC2
io->iop_ppara |= 0x00c00000;
io->iop_pdira |= 0x00400000;
io->iop_pdira &= ~0x00800000;
......
arch/ppc/Kconfig
View file @ 53ef168a
......@@ -609,7 +609,7 @@ config PPC_OF
config PPC_GEN550
bool
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS || PCORE
default y
config FORCE
......@@ -627,9 +627,14 @@ config EPIC_SERIAL_MODE
depends on 6xx && (LOPEC || SANDPOINT)
default y
config MPC10X_BRIDGE
bool
depends on PCORE || POWERPMC250 || LOPEC || SANDPOINT
default y
config MPC10X_STORE_GATHERING
bool "Enable MPC10x store gathering"
depends on FORCE || SANDPOINT
depends on MPC10X_BRIDGE
config CPC710_DATA_GATHERING
bool "Enable CPC710 data gathering"
......
arch/ppc/boot/images/Makefile
View file @ 53ef168a
......@@ -13,7 +13,7 @@ $(obj)/vmlinux.bin: vmlinux FORCE
$(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE
$(call if_changed,gzip)
quite_cmd_uimage = UIMAGE $@
quiet_cmd_uimage = UIMAGE $@
cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A ppc -O linux -T kernel \
-C gzip -a 00000000 -e 00000000 -n 'Linux-$(KERNELRELEASE)' \
-d $< $@
......
arch/ppc/boot/openfirmware/Makefile
View file @ 53ef168a
......@@ -75,7 +75,7 @@ $(obj)/image.initrd.o: $(obj)/image.o $(images)/ramdisk.image.gz FORCE
$(call if_changed,genimage-initrd)
# Create the note section for New-World PowerMacs.
quit_cmd_mknote = MKNOTE $@
quiet_cmd_mknote = MKNOTE $@
cmd_mknote = $(utils)/mknote > $@
targets += note
$(obj)/note: $(utils)/mknote FORCE
......
arch/ppc/boot/simple/misc-embedded.c
View file @ 53ef168a
......@@ -8,7 +8,6 @@
#include <linux/config.h>
#include <linux/types.h>
#include <linux/elf.h>
#include <linux/string.h>
#include <asm/bootinfo.h>
#include <asm/mmu.h>
......
arch/ppc/boot/simple/misc.c
View file @ 53ef168a
......@@ -17,7 +17,6 @@
*/
#include <linux/types.h>
#include <linux/elf.h>
#include <linux/config.h>
#include <linux/string.h>
......
arch/ppc/configs/mcpn765_defconfig
View file @ 53ef168a
This diff is collapsed.
arch/ppc/configs/pcore_defconfig
View file @ 53ef168a
This diff is collapsed.
arch/ppc/kernel/cputable.c
View file @ 53ef168a
This diff is collapsed.
arch/ppc/kernel/process.c
View file @ 53ef168a
......@@ -273,8 +273,8 @@ void show_regs(struct pt_regs * regs)
trap = TRAP(regs);
if (trap == 0x300 || trap == 0x600)
printk("DAR: %08lX, DSISR: %08lX\n", regs->dar, regs->dsisr);
printk("TASK = %p[%d] '%s' ",
current, current->pid, current->comm);
printk("TASK = %p[%d] '%s' THREAD: %p",
current, current->pid, current->comm, current->thread_info);
printk("Last syscall: %ld ", current->thread.last_syscall);
#if defined(CONFIG_4xx) && defined(DCRN_PLB0_BEAR)
......@@ -303,6 +303,16 @@ void show_regs(struct pt_regs * regs)
break;
}
printk("\n");
#ifdef CONFIG_KALLSYMS
/*
* Lookup NIP late so we have the best change of getting the
* above info out without failing
*/
printk("NIP [%08lx] ", regs->nip);
print_symbol("%s\n", regs->nip);
printk("LR [%08lx] ", regs->link);
print_symbol("%s\n", regs->link);
#endif
show_stack(current, (unsigned long *) regs->gpr[1]);
}
......
arch/ppc/kernel/signal.c
View file @ 53ef168a
......@@ -361,7 +361,7 @@ handle_rt_signal(unsigned long sig, struct k_sigaction *ka,
return;
badframe:
#if DEBUG_SIG
#ifdef DEBUG_SIG
printk("badframe in handle_rt_signal, regs=%p frame=%p newsp=%lx\n",
regs, frame, newsp);
#endif
......@@ -513,7 +513,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
return;
badframe:
#if DEBUG_SIG
#ifdef DEBUG_SIG
printk("badframe in handle_signal, regs=%p frame=%lx newsp=%lx\n",
regs, frame, *newspp);
#endif
......
arch/ppc/mm/hashtable.S
View file @ 53ef168a
......@@ -346,9 +346,9 @@ _GLOBAL(create_hpte)
rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
ori r8,r8,0xe14 /* clear out reserved bits and M */
andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
#ifdef CONFIG_SMP
BEGIN_FTR_SECTION
ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */
#endif
END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
/* Construct the high word of the PPC-style PTE (r5) */
#ifndef CONFIG_PPC64BRIDGE
......
arch/ppc/mm/ppc_mmu.c
View file @ 53ef168a
......@@ -137,10 +137,10 @@ void __init setbat(int index, unsigned long virt, unsigned long phys,
int wimgxpp;
union ubat *bat = BATS[index];
#ifdef CONFIG_SMP
if ((flags & _PAGE_NO_CACHE) == 0)
if (((flags & _PAGE_NO_CACHE) == 0) &&
(cur_cpu_spec[0]->cpu_features & CPU_FTR_NEED_COHERENT))
flags |= _PAGE_COHERENT;
#endif
bl = (size >> 17) - 1;
if (PVR_VER(mfspr(PVR)) != 1) {
/* 603, 604, etc. */
......
arch/ppc/platforms/Makefile
View file @ 53ef168a
......@@ -35,11 +35,11 @@ obj-$(CONFIG_EV64260) += ev64260_setup.o
obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o
obj-$(CONFIG_K2) += k2_setup.o k2_pci.o
obj-$(CONFIG_LOPEC) += lopec_setup.o lopec_pci.o
obj-$(CONFIG_MCPN765) += mcpn765_setup.o mcpn765_pci.o
obj-$(CONFIG_MCPN765) += mcpn765.o
obj-$(CONFIG_MENF1) += menf1_setup.o menf1_pci.o
obj-$(CONFIG_MVME5100) += mvme5100_setup.o mvme5100_pci.o
obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o
obj-$(CONFIG_PCORE) += pcore_setup.o pcore_pci.o
obj-$(CONFIG_PCORE) += pcore.o
obj-$(CONFIG_POWERPMC250) += powerpmc250.o
obj-$(CONFIG_PPLUS) += pplus.o
obj-$(CONFIG_PRPMC750) += prpmc750_setup.o prpmc750_pci.o
......
arch/ppc/platforms/gemini_setup.c
View file @ 53ef168a
......@@ -401,12 +401,12 @@ gemini_set_rtc_time( unsigned long now )
to_tm( now, &tm );
reg = gemini_rtc_read(M48T35_RTC_CONTROL);
#if DEBUG_RTC
#ifdef DEBUG_RTC
printk("set rtc: reg = %x\n", reg);
#endif
gemini_rtc_write((reg|M48T35_RTC_SET), M48T35_RTC_CONTROL);
#if DEBUG_RTC
#ifdef DEBUG_RTC
printk("set rtc: tm vals - sec=%x, min=%x, hour=%x, mon=%x, mday=%x, year=%x\n",
tm.tm_sec, tm.tm_min, tm.tm_hour, tm.tm_mon, tm.tm_mday, tm.tm_year);
#endif
......
arch/ppc/platforms/mcpn765_pci.c deleted 100644 → 0
View file @ 9fa12b00
/*
* arch/ppc/platforms/mcpn765_pci.c
*
* PCI setup routines for the Motorola MCG MCPN765 cPCI board.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/pplus.h>
#include "mcpn765.h"
/*
* Motorola MCG MCPN765 interrupt routing.
*/
static inline int
mcpn765_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{ 14, 0, 0, 0 }, /* IDSEL 11 - have to manually set */
{ 0, 0, 0, 0 }, /* IDSEL 12 - unused */
{ 0, 0, 0, 0 }, /* IDSEL 13 - unused */
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 0 */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
{ 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */
{ 0, 0, 0, 0 }, /* IDSEL 18 - PMC 2B Connector XXXX */
{ 29, 0, 0, 0 }, /* IDSEL 19 - Enet 1 */
{ 20, 0, 0, 0 }, /* IDSEL 20 - 21554 cPCI bridge */
};
const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
void __init
mcpn765_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = MCPN765_PCI_PHY_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
MCPN765_PCI_IO_START,
MCPN765_PCI_IO_END,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
MCPN765_PCI_MEM_START,
MCPN765_PCI_MEM_END,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = MCPN765_PCI_IO_START;
hose->io_space.end = MCPN765_PCI_IO_END;
hose->mem_space.start = MCPN765_PCI_MEM_START;
hose->mem_space.end = MCPN765_PCI_MEM_END - PPLUS_MPIC_SIZE;
if (pplus_init(hose,
MCPN765_HAWK_PPC_REG_BASE,
MCPN765_PROC_PCI_MEM_START,
MCPN765_PROC_PCI_MEM_END - PPLUS_MPIC_SIZE,
MCPN765_PROC_PCI_IO_START,
MCPN765_PROC_PCI_IO_END,
MCPN765_PCI_MEM_END - PPLUS_MPIC_SIZE + 1) != 0) {
printk("Could not initialize HAWK bridge\n");
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mcpn765_map_irq;
return;
}
arch/ppc/platforms/pcore_setup.c → arch/ppc/platforms/pcore.c
View file @ 53ef168a
......@@ -23,16 +23,10 @@
#include <linux/major.h>
#include <linux/initrd.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/ide.h>
#include <linux/root_dev.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/time.h>
......@@ -40,14 +34,122 @@
#include <asm/mpc10x.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include <asm/kgdb.h>
#include "pcore.h"
extern int pcore_find_bridges(void);
extern unsigned long loops_per_jiffy;
static int board_type;
static inline int __init
pcore_6750_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{9, 10, 11, 12}, /* IDSEL 24 - DEC 21554 */
{10, 0, 0, 0}, /* IDSEL 25 - DEC 21143 */
{11, 12, 9, 10}, /* IDSEL 26 - PMC I */
{12, 9, 10, 11}, /* IDSEL 27 - PMC II */
{0, 0, 0, 0}, /* IDSEL 28 - unused */
{0, 0, 9, 0}, /* IDSEL 29 - unused */
{0, 0, 0, 0}, /* IDSEL 30 - Winbond */
};
const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
};
static inline int __init
pcore_680_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{9, 10, 11, 12}, /* IDSEL 24 - Sentinel */
{10, 0, 0, 0}, /* IDSEL 25 - i82559 #1 */
{11, 12, 9, 10}, /* IDSEL 26 - PMC I */
{12, 9, 10, 11}, /* IDSEL 27 - PMC II */
{9, 0, 0, 0}, /* IDSEL 28 - i82559 #2 */
{0, 0, 0, 0}, /* IDSEL 29 - unused */
{0, 0, 0, 0}, /* IDSEL 30 - Winbond */
};
const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
};
void __init
pcore_pcibios_fixup(void)
{
struct pci_dev *dev;
if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_83C553,
0)))
{
/* Reroute interrupts both IDE channels to 15 */
pci_write_config_byte(dev,
PCORE_WINBOND_IDE_INT,
0xff);
/* Route INTA-D to IRQ9-12, respectively */
pci_write_config_word(dev,
PCORE_WINBOND_PCI_INT,
0x9abc);
/*
* Set up 8259 edge/level triggering
*/
outb(0x00, PCORE_WINBOND_PRI_EDG_LVL);
outb(0x1e, PCORE_WINBOND_SEC_EDG_LVL);
}
}
int __init
pcore_find_bridges(void)
{
struct pci_controller* hose;
int host_bridge, board_type;
hose = pcibios_alloc_controller();
if (!hose)
return 0;
mpc10x_bridge_init(hose,
MPC10X_MEM_MAP_B,
MPC10X_MEM_MAP_B,
MPC10X_MAPB_EUMB_BASE);
/* Determine board type */
early_read_config_dword(hose,
0,
PCI_DEVFN(0,0),
PCI_VENDOR_ID,
&host_bridge);
if (host_bridge == MPC10X_BRIDGE_106)
board_type = PCORE_TYPE_6750;
else /* MPC10X_BRIDGE_107 */
board_type = PCORE_TYPE_680;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = pcore_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
if (board_type == PCORE_TYPE_6750)
ppc_md.pci_map_irq = pcore_6750_map_irq;
else /* PCORE_TYPE_680 */
ppc_md.pci_map_irq = pcore_680_map_irq;
return board_type;
}
/* Dummy variable to satisfy mpc10x_common.o */
void *OpenPIC_Addr;
......@@ -130,7 +232,14 @@ pcore_setup_arch(void)
conswitchp = &dummy_con;
#endif
printk("Force PCore port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
printk(KERN_INFO "Force PowerCore ");
if (board_type == PCORE_TYPE_6750)
printk("6750\n");
else
printk("680\n");
printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
_set_L2CR(L2CR_L2E | _get_L2CR());
}
static void
......@@ -175,25 +284,16 @@ pcore_init_IRQ(void)
static __inline__ void
pcore_set_bat(void)
{
unsigned long bat3u, bat3l;
__asm__ __volatile__(
" lis %0,0xf000\n \
ori %1,%0,0x002a\n \
ori %0,%0,0x1ffe\n \
mtspr 0x21e,%0\n \
mtspr 0x21f,%1\n \
isync\n \
sync "
: "=r" (bat3u), "=r" (bat3l));
mb();
mtspr(DBAT3U, 0xf0001ffe);
mtspr(DBAT3L, 0xfe80002a);
mb();
}
static unsigned long __init
pcore_find_end_of_memory(void)
{
/* Cover I/O space with a BAT */
/* yuck, better hope your ram size is a power of 2 -- paulus */
pcore_set_bat();
return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
}
......@@ -212,6 +312,10 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
{
parse_bootinfo(find_bootinfo());
/* Cover I/O space with a BAT */
/* yuck, better hope your ram size is a power of 2 -- paulus */
pcore_set_bat();
isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
......@@ -241,4 +345,11 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = gen550_progress;
#endif
#ifdef CONFIG_KGDB
ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
#endif
}
arch/ppc/platforms/pcore_pci.c deleted 100644 → 0
View file @ 9fa12b00
/*
* arch/ppc/platforms/pcore_pci.c
*
* PCI support for Force PCORE boards
*
* Author: Matt Porter <mporter@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/mpc10x.h>
#include "pcore.h"
#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif /* DEBUG */
static inline int __init
pcore_6750_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{9, 10, 11, 12}, /* IDSEL 24 - DEC 21554 */
{10, 0, 0, 0}, /* IDSEL 25 - DEC 21143 */
{11, 12, 9, 10}, /* IDSEL 26 - PMC I */
{12, 9, 10, 11}, /* IDSEL 27 - PMC II */
{0, 0, 0, 0}, /* IDSEL 28 - unused */
{0, 0, 9, 0}, /* IDSEL 29 - unused */
{0, 0, 0, 0}, /* IDSEL 30 - Winbond */
};
const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
};
static inline int __init
pcore_680_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{9, 10, 11, 12}, /* IDSEL 24 - Sentinel */
{10, 0, 0, 0}, /* IDSEL 25 - i82559 #1 */
{11, 12, 9, 10}, /* IDSEL 26 - PMC I */
{12, 9, 10, 11}, /* IDSEL 27 - PMC II */
{9, 0, 0, 0}, /* IDSEL 28 - i82559 #2 */
{0, 0, 0, 0}, /* IDSEL 29 - unused */
{0, 0, 0, 0}, /* IDSEL 30 - Winbond */
};
const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
};
void __init
pcore_pcibios_fixup(void)
{
struct pci_dev *dev;
if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_83C553,
0)))
{
/* Reroute interrupts both IDE channels to 15 */
pci_write_config_byte(dev,
PCORE_WINBOND_IDE_INT,
0xff);
/* Route INTA-D to IRQ9-12, respectively */
pci_write_config_word(dev,
PCORE_WINBOND_PCI_INT,
0x9abc);
/*
* Set up 8259 edge/level triggering
*/
outb(0x00, PCORE_WINBOND_PRI_EDG_LVL);
outb(0x1e, PCORE_WINBOND_SEC_EDG_LVL);
}
}
int __init
pcore_find_bridges(void)
{
struct pci_controller* hose;
int host_bridge, board_type;
hose = pcibios_alloc_controller();
if (!hose)
return 0;
mpc10x_bridge_init(hose,
MPC10X_MEM_MAP_B,
MPC10X_MEM_MAP_B,
MPC10X_MAPB_EUMB_BASE);
/* Determine board type */
early_read_config_dword(hose,
0,
PCI_DEVFN(0,0),
PCI_VENDOR_ID,
&host_bridge);
if (host_bridge == MPC10X_BRIDGE_106)
board_type = PCORE_TYPE_6750;
else /* MPC10X_BRIDGE_107 */
board_type = PCORE_TYPE_680;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = pcore_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
if (board_type == PCORE_TYPE_6750)
ppc_md.pci_map_irq = pcore_6750_map_irq;
else /* PCORE_TYPE_680 */
ppc_md.pci_map_irq = pcore_680_map_irq;
return board_type;
}
arch/ppc/platforms/pplus.c
View file @ 53ef168a
......@@ -513,7 +513,7 @@ void __init pplus_find_bridges(void)
hose->mem_space.start = PPLUS_PCI_MEM_START;
hose->mem_space.end = PPLUS_PCI_MEM_END - HAWK_MPIC_SIZE;
if (pplus_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START,
if (hawk_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START,
PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
PPLUS_PROC_PCI_IO_START, PPLUS_PROC_PCI_IO_END,
PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
......@@ -816,7 +816,7 @@ static unsigned long __init pplus_find_end_of_memory(void)
dump_dbats();
#endif
total = pplus_get_mem_size(PPLUS_HAWK_SMC_BASE);
total = hawk_get_mem_size(PPLUS_HAWK_SMC_BASE);
return (total);
}
......
arch/ppc/platforms/pplus.h
View file @ 53ef168a
......@@ -64,14 +64,4 @@
#define PPLUS_VGA_MEM_BASE 0xf0000000U
extern int pplus_init(struct pci_controller *hose,
unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
unsigned long processor_pci_mem_end,
unsigned long processor_pci_io_start,
unsigned long processor_pci_io_end,
unsigned long processor_mpic_base);
extern unsigned long pplus_get_mem_size(unsigned int smc_base);
extern int pplus_mpic_init(unsigned int pci_mem_offset);
#endif /* __PPC_PPLUS_H */
#endif /* __PPC_PPLUS_H */
arch/ppc/platforms/prep_pci.c
View file @ 53ef168a
......@@ -311,11 +311,11 @@ static char Genesis2_pci_IRQ_map[23] __prepdata =
0, /* Slot 7 - unused */
0, /* Slot 8 - unused */
0, /* Slot 9 - unused */
0, /* Slot 10 - Ethernet */
0, /* Slot 11 - Universe PCI - VME Bridge */
3, /* Slot 12 - unused */
0, /* Slot 13 - unused */
2, /* Slot 14 - SCSI */
0, /* Slot 10 - unused */
0, /* Slot 11 - IDE */
3, /* Slot 12 - SCSI */
5, /* Slot 13 - Universe PCI - VME Bridge */
2, /* Slot 14 - Ethernet */
0, /* Slot 15 - unused */
9, /* Slot 16 - PMC 1 */
12, /* Slot 17 - pci */
......
arch/ppc/platforms/prep_setup.c
View file @ 53ef168a
......@@ -323,7 +323,7 @@ prep_carolina_cpuinfo(struct seq_file *m)
/* L2 size */
if ((l2_reg & 0x60) == 0)
seq_printf(m, "256KiB");
else if ((l2_reg & 0x60) == 1)
else if ((l2_reg & 0x60) == 0x20)
seq_printf(m, "512KiB");
else
seq_printf(m, "unknown size");
......@@ -725,6 +725,7 @@ prep_setup_arch(void)
case PREP_IBM_CAROLINA_IDE_0:
case PREP_IBM_CAROLINA_IDE_1:
case PREP_IBM_CAROLINA_IDE_2:
case PREP_IBM_CAROLINA_IDE_3:
is_ide = 1;
case PREP_IBM_CAROLINA_SCSI_0:
case PREP_IBM_CAROLINA_SCSI_1:
......
arch/ppc/syslib/Makefile
View file @ 53ef168a
......@@ -42,28 +42,24 @@ obj-$(CONFIG_EV64260) += gt64260_common.o gt64260_pic.o \
obj-$(CONFIG_GEMINI) += open_pic.o i8259.o indirect_pci.o
obj-$(CONFIG_K2) += i8259.o indirect_pci.o todc_time.o \
pci_auto.o
obj-$(CONFIG_LOPEC) += mpc10x_common.o indirect_pci.o pci_auto.o \
open_pic.o i8259.o todc_time.o
obj-$(CONFIG_LOPEC) += pci_auto.o open_pic.o i8259.o todc_time.o
obj-$(CONFIG_MCPN765) += todc_time.o indirect_pci.o pci_auto.o \
open_pic.o i8259.o pplus_common.o
open_pic.o i8259.o hawk_common.o
obj-$(CONFIG_MENF1) += todc_time.o i8259.o mpc10x_common.o \
pci_auto.o indirect_pci.o
obj-$(CONFIG_MVME5100) += open_pic.o todc_time.o indirect_pci.o \
i8259.o pci_auto.o pplus_common.o
i8259.o pci_auto.o hawk_common.o
obj-$(CONFIG_OCOTEA) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_PAL4) += cpc700_pic.o
obj-$(CONFIG_PCORE) += mpc10x_common.o todc_time.o i8259.o \
indirect_pci.o pci_auto.o
obj-$(CONFIG_POWERPMC250) += open_pic.o mpc10x_common.o \
indirect_pci.o pci_auto.o
obj-$(CONFIG_PPLUS) += pplus_common.o open_pic.o i8259.o \
obj-$(CONFIG_PCORE) += todc_time.o i8259.o pci_auto.o
obj-$(CONFIG_POWERPMC250) += open_pic.o pci_auto.o
obj-$(CONFIG_PPLUS) += hawk_common.o open_pic.o i8259.o \
indirect_pci.o todc_time.o pci_auto.o
obj-$(CONFIG_PRPMC750) += open_pic.o indirect_pci.o pci_auto.o \
pplus_common.o
hawk_common.o
obj-$(CONFIG_PRPMC800) += open_pic.o indirect_pci.o pci_auto.o \
pplus_common.o harrier.o
obj-$(CONFIG_SANDPOINT) += i8259.o open_pic.o mpc10x_common.o \
pci_auto.o indirect_pci.o todc_time.o
hawk_common.o harrier.o
obj-$(CONFIG_SANDPOINT) += i8259.o open_pic.o pci_auto.o todc_time.o
obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_8260) += m8260_setup.o ppc8260_pic.o
......@@ -72,3 +68,4 @@ obj-$(CONFIG_KGDB) += gen550_kgdb.o gen550_dbg.o
obj-$(CONFIG_SERIAL_TEXT_DEBUG) += gen550_dbg.o
endif
obj-$(CONFIG_BOOTX_TEXT) += btext.o
obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o indirect_pci.o
arch/ppc/syslib/pplus_common.c → arch/ppc/syslib/hawk_common.c
View file @ 53ef168a
/*
* arch/ppc/syslib/pplus_common.c
* arch/ppc/syslib/hawk_common.c
*
* Common Motorola PowerPlus Platform--really Falcon/Raven or HAWK.
*
......@@ -44,7 +44,7 @@
* 'OpenPIC_Addr' will be set correctly by this routine.
*/
int __init
pplus_init(struct pci_controller *hose,
hawk_init(struct pci_controller *hose,
uint ppc_reg_base,
ulong processor_pci_mem_start,
ulong processor_pci_mem_end,
......@@ -59,14 +59,14 @@ pplus_init(struct pci_controller *hose,
*/
if (((processor_pci_mem_start&0xffff0000) != processor_pci_mem_start) ||
((processor_pci_io_start &0xffff0000) != processor_pci_io_start)) {
printk("pplus_init: %s\n",
printk("hawk_init: %s\n",
"PPC to PCI mappings must start on 64 KB boundaries");
return -1;
}
if (((processor_pci_mem_end &0x0000ffff) != 0x0000ffff) ||
((processor_pci_io_end &0x0000ffff) != 0x0000ffff)) {
printk("pplus_init: PPC to PCI mappings %s\n",
printk("hawk_init: PPC to PCI mappings %s\n",
"must end just before a 64 KB boundaries");
return -1;
}
......@@ -75,19 +75,19 @@ pplus_init(struct pci_controller *hose,
(hose->mem_space.end - hose->mem_space.start)) ||
((processor_pci_io_end - processor_pci_io_start) !=
(hose->io_space.end - hose->io_space.start))) {
printk("pplus_init: %s\n",
printk("hawk_init: %s\n",
"PPC and PCI memory or I/O space sizes don't match");
return -1;
}
if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) {
printk("pplus_init: %s\n",
printk("hawk_init: %s\n",
"MPIC address must start on 256 MB boundary");
return -1;
}
if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) {
printk("pplus_init: %s\n",
printk("hawk_init: %s\n",
"pci_dram_offset must be multiple of 64 KB");
return -1;
}
......@@ -226,7 +226,7 @@ static uint hawk_size_table[] __initdata = {
* into virtual memory--too early to use ioremap().
*/
unsigned long __init
pplus_get_mem_size(uint smc_base)
hawk_get_mem_size(uint smc_base)
{
unsigned long total;
int i, size_table_entries, reg_limit;
......@@ -238,7 +238,7 @@ pplus_get_mem_size(uint smc_base)
vend_dev_id = in_be32((uint *)smc_base + PCI_VENDOR_ID);
if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) {
printk("pplus_get_mem_size: %s (0x%x)\n",
printk("hawk_get_mem_size: %s (0x%x)\n",
"Not a Motorola Memory Controller", vend_dev_id);
return 0;
}
......@@ -259,7 +259,7 @@ pplus_get_mem_size(uint smc_base)
reg_limit = HAWK_SMC_REG_COUNT;
}
else {
printk("pplus_get_mem_size: %s (0x%x)\n",
printk("hawk_get_mem_size: %s (0x%x)\n",
"Not a Falcon or HAWK", vend_dev_id);
return 0;
}
......@@ -285,35 +285,3 @@ pplus_get_mem_size(uint smc_base)
return total;
}
int __init
pplus_mpic_init(unsigned int pci_mem_offset)
{
unsigned short devid;
unsigned int pci_membase;
/* Check the first PCI device to see if it is a Raven or Hawk. */
early_read_config_word(0, 0, 0, PCI_DEVICE_ID, &devid);
switch (devid) {
case PCI_DEVICE_ID_MOTOROLA_RAVEN:
case PCI_DEVICE_ID_MOTOROLA_HAWK:
break;
default:
OpenPIC_Addr = NULL;
return 1;
}
/* Read the memory base register. */
early_read_config_dword(0, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
if (pci_membase == 0) {
OpenPIC_Addr = NULL;
return 1;
}
/* Map the MPIC registers to virtual memory. */
OpenPIC_Addr = ioremap(pci_membase + pci_mem_offset, 0x22000);
return 0;
}
include/asm-ppc/cputable.h
View file @ 53ef168a
......@@ -75,6 +75,7 @@ extern struct cpu_spec *cur_cpu_spec[];
#define CPU_FTR_DUAL_PLL_750FX 0x00004000
#define CPU_FTR_NO_DPM 0x00008000
#define CPU_FTR_HAS_HIGH_BATS 0x00010000
#define CPU_FTR_NEED_COHERENT 0x00020000
#ifdef __ASSEMBLY__
......
include/asm-ppc/hawk.h
View file @ 53ef168a
......@@ -29,4 +29,4 @@ extern int hawk_init(struct pci_controller *hose,
extern unsigned long hawk_get_mem_size(unsigned int smc_base);
extern int hawk_mpic_init(unsigned int pci_mem_offset);
#endif /* __ASMPPC_PPLUS_H */
#endif /* __ASMPPC_HAWK_H */
include/asm-ppc/highmem.h
View file @ 53ef168a
......@@ -87,7 +87,7 @@ static inline void *kmap_atomic(struct page *page, enum km_type type)
idx = type + KM_TYPE_NR*smp_processor_id();
vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE;
#if HIGHMEM_DEBUG
#ifdef HIGHMEM_DEBUG
BUG_ON(!pte_none(*(kmap_pte+idx)));
#endif
set_pte(kmap_pte+idx, mk_pte(page, kmap_prot));
......@@ -98,7 +98,7 @@ static inline void *kmap_atomic(struct page *page, enum km_type type)
static inline void kunmap_atomic(void *kvaddr, enum km_type type)
{
#if HIGHMEM_DEBUG
#ifdef HIGHMEM_DEBUG
unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
unsigned int idx = type + KM_TYPE_NR*smp_processor_id();
......
include/asm-ppc/rwsem.h
View file @ 53ef168a
......@@ -27,7 +27,7 @@ struct rw_semaphore {
#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
spinlock_t wait_lock;
struct list_head wait_list;
#if RWSEM_DEBUG
#ifdef RWSEM_DEBUG
int debug;
#endif
};
......@@ -35,7 +35,7 @@ struct rw_semaphore {
/*
* initialisation
*/
#if RWSEM_DEBUG
#ifdef RWSEM_DEBUG
#define __RWSEM_DEBUG_INIT , 0
#else
#define __RWSEM_DEBUG_INIT /* */
......@@ -59,7 +59,7 @@ static inline void init_rwsem(struct rw_semaphore *sem)
sem->count = RWSEM_UNLOCKED_VALUE;
spin_lock_init(&sem->wait_lock);
INIT_LIST_HEAD(&sem->wait_list);
#if RWSEM_DEBUG
#ifdef RWSEM_DEBUG
sem->debug = 0;
#endif
}
......
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