Commit 556e2f60 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A handful of clk driver fixes and one core framework fix

   - Do a DT/firmware lookup in clk_core_get() even when the DT index is
     a nonsensical value

   - Fix some clk data typos in the Amlogic DT headers/code

   - Avoid returning junk in the TI clk driver when an invalid clk is
     looked for

   - Fix dividers for the emac clks on Stratix10 SoCs

   - Fix default HDA rates on Tegra210 to correct distorted audio"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: socfpga: stratix10: fix divider entry for the emac clocks
  clk: Do a DT parent lookup even when index < 0
  clk: tegra210: Fix default rates for HDA clocks
  clk: ti: clkctrl: Fix returning uninitialized data
  clk: meson: meson8b: fix a typo in the VPU parent names array variable
  clk: meson: fix MPLL 50M binding id typo
parents 65ee21eb 74684cce
...@@ -368,7 +368,7 @@ static struct clk_core *clk_core_get(struct clk_core *core, u8 p_index) ...@@ -368,7 +368,7 @@ static struct clk_core *clk_core_get(struct clk_core *core, u8 p_index)
const char *dev_id = dev ? dev_name(dev) : NULL; const char *dev_id = dev ? dev_name(dev) : NULL;
struct device_node *np = core->of_node; struct device_node *np = core->of_node;
if (np && index >= 0) if (np && (name || index >= 0))
hw = of_clk_get_hw(np, index, name); hw = of_clk_get_hw(np, index, name);
/* /*
......
...@@ -2734,8 +2734,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { ...@@ -2734,8 +2734,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
[CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
[CLKID_MALI_1] = &g12a_mali_1.hw, [CLKID_MALI_1] = &g12a_mali_1.hw,
[CLKID_MALI] = &g12a_mali.hw, [CLKID_MALI] = &g12a_mali.hw,
[CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw, [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
[CLKID_MPLL_5OM] = &g12a_mpll_50m.hw, [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
......
...@@ -166,7 +166,7 @@ ...@@ -166,7 +166,7 @@
#define CLKID_HDMI_DIV 167 #define CLKID_HDMI_DIV 167
#define CLKID_MALI_0_DIV 170 #define CLKID_MALI_0_DIV 170
#define CLKID_MALI_1_DIV 173 #define CLKID_MALI_1_DIV 173
#define CLKID_MPLL_5OM_DIV 176 #define CLKID_MPLL_50M_DIV 176
#define CLKID_SYS_PLL_DIV16_EN 178 #define CLKID_SYS_PLL_DIV16_EN 178
#define CLKID_SYS_PLL_DIV16 179 #define CLKID_SYS_PLL_DIV16 179
#define CLKID_CPU_CLK_DYN0_SEL 180 #define CLKID_CPU_CLK_DYN0_SEL 180
......
...@@ -1761,7 +1761,7 @@ static struct clk_regmap meson8m2_gp_pll = { ...@@ -1761,7 +1761,7 @@ static struct clk_regmap meson8m2_gp_pll = {
}, },
}; };
static const char * const mmeson8b_vpu_0_1_parent_names[] = { static const char * const meson8b_vpu_0_1_parent_names[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
}; };
...@@ -1778,8 +1778,8 @@ static struct clk_regmap meson8b_vpu_0_sel = { ...@@ -1778,8 +1778,8 @@ static struct clk_regmap meson8b_vpu_0_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_0_sel", .name = "vpu_0_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = mmeson8b_vpu_0_1_parent_names, .parent_names = meson8b_vpu_0_1_parent_names,
.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names), .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
...@@ -1837,8 +1837,8 @@ static struct clk_regmap meson8b_vpu_1_sel = { ...@@ -1837,8 +1837,8 @@ static struct clk_regmap meson8b_vpu_1_sel = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "vpu_1_sel", .name = "vpu_1_sel",
.ops = &clk_regmap_mux_ops, .ops = &clk_regmap_mux_ops,
.parent_names = mmeson8b_vpu_0_1_parent_names, .parent_names = meson8b_vpu_0_1_parent_names,
.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names), .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
}, },
}; };
......
...@@ -103,9 +103,9 @@ static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = { ...@@ -103,9 +103,9 @@ static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
{ STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), { STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
0, 0, 0, 0x3C, 1}, 0, 0, 0, 0x3C, 1},
{ STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux), { STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
0, 0, 4, 0xB0, 0}, 0, 0, 2, 0xB0, 0},
{ STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux), { STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
0, 0, 4, 0xB0, 1}, 0, 0, 2, 0xB0, 1},
{ STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux, { STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 4, 0xB0, 2}, ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 4, 0xB0, 2},
{ STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux, { STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
......
...@@ -3366,6 +3366,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { ...@@ -3366,6 +3366,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
{ TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
{ TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
{ TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
/* This MUST be the last entry. */ /* This MUST be the last entry. */
{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
}; };
......
...@@ -229,6 +229,7 @@ static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec, ...@@ -229,6 +229,7 @@ static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
{ {
struct omap_clkctrl_provider *provider = data; struct omap_clkctrl_provider *provider = data;
struct omap_clkctrl_clk *entry; struct omap_clkctrl_clk *entry;
bool found = false;
if (clkspec->args_count != 2) if (clkspec->args_count != 2)
return ERR_PTR(-EINVAL); return ERR_PTR(-EINVAL);
...@@ -238,11 +239,13 @@ static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec, ...@@ -238,11 +239,13 @@ static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
list_for_each_entry(entry, &provider->clocks, node) { list_for_each_entry(entry, &provider->clocks, node) {
if (entry->reg_offset == clkspec->args[0] && if (entry->reg_offset == clkspec->args[0] &&
entry->bit_offset == clkspec->args[1]) entry->bit_offset == clkspec->args[1]) {
found = true;
break; break;
}
} }
if (!entry) if (!found)
return ERR_PTR(-EINVAL); return ERR_PTR(-EINVAL);
return entry->clk; return entry->clk;
......
...@@ -130,7 +130,7 @@ ...@@ -130,7 +130,7 @@
#define CLKID_MALI_1_SEL 172 #define CLKID_MALI_1_SEL 172
#define CLKID_MALI_1 174 #define CLKID_MALI_1 174
#define CLKID_MALI 175 #define CLKID_MALI 175
#define CLKID_MPLL_5OM 177 #define CLKID_MPLL_50M 177
#define CLKID_CPU_CLK 187 #define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201 #define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204 #define CLKID_VDEC_1 204
......
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