Commit 55d42d27 authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo

perf vendor events: Add KnightsLanding V9 event file

Add a Intel event file for perf.
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-3x2we5evro8uhwmergz1mbd7@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 902ea4ee
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[
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all instruction fetches, including uncacheable fetches."
},
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all instruction fetches that hit the instruction cache."
},
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding."
},
{
"EventCode": "0xE7",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MS_DECODED.MS_ENTRY",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times the MSROM starts a flow of uops."
}
]
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[
{
"PEBS": "1",
"EventCode": "0x04",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of load micro-ops retired that cause a DTLB miss",
"Data_LA": "1"
},
{
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
"SampleAfterValue": "100003",
"BriefDescription": "Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted",
"EdgeDetect": "1"
},
{
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included."
},
{
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
"SampleAfterValue": "100003",
"BriefDescription": "Counts the total I-side page walks that are completed.",
"EdgeDetect": "1"
},
{
"PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress. ",
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included."
},
{
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "PAGE_WALKS.WALKS",
"SampleAfterValue": "100003",
"BriefDescription": "Counts the total page walks that are completed (I-side and D-side)",
"EdgeDetect": "1"
},
{
"PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.",
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included."
}
]
\ No newline at end of file
...@@ -16,3 +16,4 @@ GenuineIntel-6-3F,v17,haswellx,core ...@@ -16,3 +16,4 @@ GenuineIntel-6-3F,v17,haswellx,core
GenuineIntel-6-3A,v18,ivybridge,core GenuineIntel-6-3A,v18,ivybridge,core
GenuineIntel-6-3E,v19,ivytown,core GenuineIntel-6-3E,v19,ivytown,core
GenuineIntel-6-2D,v20,jaketown,core GenuineIntel-6-2D,v20,jaketown,core
GenuineIntel-6-57,v9,knightslanding,core
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