Commit 564ee46f authored by Sebastian Andrzej Siewior's avatar Sebastian Andrzej Siewior Committed by Kumar Gala

powerpc/85xx: p2020rdb & p1010rdb - lower spi flash freq to 40Mhz

This is here most likely since the FSL bsp. Back in the FSL bsp it was
set to 50Mhz and working. However the driver divided the SoC freq. only
by 2. According to the TRM the platform clock (which the manual refers
in its formula) is the system clock divided by two. So in the end it has
to divide by 4 and this is what the fsl-spi driver in tree is doing.
Since then the flash is not wokring I guess. After chaning the freq from
50Mhz to 40Mhz like others do then I can access the flash.
Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 0c00f656
...@@ -138,7 +138,7 @@ flash@0 { ...@@ -138,7 +138,7 @@ flash@0 {
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801";
reg = <0>; reg = <0>;
spi-max-frequency = <50000000>; spi-max-frequency = <40000000>;
partition@0 { partition@0 {
/* 1MB for u-boot Bootloader Image */ /* 1MB for u-boot Bootloader Image */
......
...@@ -157,7 +157,7 @@ flash@0 { ...@@ -157,7 +157,7 @@ flash@0 {
#size-cells = <1>; #size-cells = <1>;
compatible = "spansion,s25sl12801"; compatible = "spansion,s25sl12801";
reg = <0>; reg = <0>;
spi-max-frequency = <50000000>; spi-max-frequency = <40000000>;
partition@0 { partition@0 {
/* 512KB for u-boot Bootloader Image */ /* 512KB for u-boot Bootloader Image */
......
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