Commit 5694785c authored by Jean Delvare's avatar Jean Delvare Committed by Alex Deucher

drm/amdgpu: Fix undue fallthroughs in golden registers initialization

As I was staring at the si_init_golden_registers code, I noticed that
the Pitcairn initialization silently falls through the Cape Verde
initialization, and the Oland initialization falls through the Hainan
initialization. However there is no comment stating that this is
intentional, and the radeon driver doesn't have any such fallthrough,
so I suspect this is not supposed to happen.
Signed-off-by: default avatarJean Delvare <jdelvare@suse.de>
Fixes: 62a37553 ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang <Qingqing.Wang@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Marek Olšák" <maraeo@gmail.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent c471e70b
...@@ -1385,6 +1385,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev) ...@@ -1385,6 +1385,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
pitcairn_mgcg_cgcg_init, pitcairn_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
break;
case CHIP_VERDE: case CHIP_VERDE:
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
verde_golden_registers, verde_golden_registers,
...@@ -1409,6 +1410,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev) ...@@ -1409,6 +1410,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
oland_mgcg_cgcg_init, oland_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
break;
case CHIP_HAINAN: case CHIP_HAINAN:
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
hainan_golden_registers, hainan_golden_registers,
......
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