Commit 56c6855c authored by Thor Thayer's avatar Thor Thayer Committed by Boris Brezillon

mtd: spi-nor: Add Micron MT25QU02 support

Add support for a new Micron 2Gb Flash memory part.
Datasheet is available: mt25q_qlkt_l_02g_cbb_0.pdf

Testing was done on a Stratix10 SoCFPGA Development Kit.
Reported-by: default avatarSujith Chidurala <sujith.chakra.chidurala@intel.com>
Tested-by: default avatarPaul Kim <paul.kim@intel.com>
Signed-off-by: default avatarThor Thayer <thor.thayer@linux.intel.com>
Acked-by: default avatarMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@bootlin.com>
parent 60cc43fc
...@@ -1087,6 +1087,7 @@ static const struct flash_info spi_nor_ids[] = { ...@@ -1087,6 +1087,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
/* PMC */ /* PMC */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
......
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