Commit 575bc7b4 authored by Sascha Hauer's avatar Sascha Hauer Committed by Heiko Stuebner

dt-bindings: clock: rockchip: add USB480M_PHY mux

The USB480M clock can source from a MUX that selects the clock to come
from either of the USB-phy internal 480MHz PLLs. These clocks are
provided by the USB phy driver. This adds the define for it.
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240405-clk-rk3568-usb480m-phy-mux-v1-1-6c89de20a6ff@pengutronix.deSigned-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 4cece764
...@@ -78,6 +78,7 @@ ...@@ -78,6 +78,7 @@
#define CPLL_333M 9 #define CPLL_333M 9
#define ARMCLK 10 #define ARMCLK 10
#define USB480M 11 #define USB480M 11
#define USB480M_PHY 12
#define ACLK_CORE_NIU2BUS 18 #define ACLK_CORE_NIU2BUS 18
#define CLK_CORE_PVTM 19 #define CLK_CORE_PVTM 19
#define CLK_CORE_PVTM_CORE 20 #define CLK_CORE_PVTM_CORE 20
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment