Commit 58247b9f authored by Dmitry Rokosov's avatar Dmitry Rokosov Committed by Vinod Koul

phy: amlogic: enable/disable clkin during Amlogic USB PHY init/exit

Previously, all Amlogic boards used the XTAL clock as the default board
clock for the USB PHY input, so there was no need to enable it.
However, with the introduction of new Amlogic SoCs like the A1 family,
the USB PHY now uses a gated clock. Hence, it is necessary to enable
this gated clock during the PHY initialization sequence, or disable it
during the PHY exit, as appropriate.
Signed-off-by: default avatarDmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20230426102922.19705-2-ddrokosov@sberdevices.ruSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent ac9a7868
......@@ -172,10 +172,16 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
int ret;
unsigned int value;
ret = reset_control_reset(priv->reset);
ret = clk_prepare_enable(priv->clk);
if (ret)
return ret;
ret = reset_control_reset(priv->reset);
if (ret) {
clk_disable_unprepare(priv->clk);
return ret;
}
udelay(RESET_COMPLETE_TIME);
/* usb2_otg_aca_en == 0 */
......@@ -277,8 +283,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
static int phy_meson_g12a_usb2_exit(struct phy *phy)
{
struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
int ret;
ret = reset_control_reset(priv->reset);
if (!ret)
clk_disable_unprepare(priv->clk);
return reset_control_reset(priv->reset);
return ret;
}
/* set_mode is not needed, mode setting is handled via the UTMI bus */
......
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