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Commit 586893eb authored by Russell King's avatar Russell King
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Merge branch 'for-rmk' of... 

Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable

Conflicts:
	arch/arm/Kconfig
	arch/arm/mach-exynos4/mach-nuri.c
parents 014322da bd6356bd
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Showing with 226 additions and 2940 deletions
Documentation/arm/Samsung/Overview.txt
View file @ 586893eb
......@@ -14,7 +14,6 @@ Introduction
- S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list
- S3C64XX: S3C6400 and S3C6410
- S5P6440
- S5P6442
- S5PC100
- S5PC110 / S5PV210
......@@ -36,7 +35,6 @@ Configuration
unifying all the SoCs into one kernel.
s5p6440_defconfig - S5P6440 specific default configuration
s5p6442_defconfig - S5P6442 specific default configuration
s5pc100_defconfig - S5PC100 specific default configuration
s5pc110_defconfig - S5PC110 specific default configuration
s5pv210_defconfig - S5PV210 specific default configuration
......
arch/arm/Kconfig
View file @ 586893eb
......@@ -730,16 +730,6 @@ config ARCH_S5P64X0
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
SMDK6450.
config ARCH_S5P6442
bool "Samsung S5P6442"
select CPU_V6
select GENERIC_GPIO
select HAVE_CLK
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5P6442 CPU based systems
config ARCH_S5PC100
bool "Samsung S5PC100"
select GENERIC_GPIO
......@@ -991,8 +981,6 @@ endif
source "arch/arm/mach-s5p64x0/Kconfig"
source "arch/arm/mach-s5p6442/Kconfig"
source "arch/arm/mach-s5pc100/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig"
......@@ -1420,7 +1408,7 @@ source kernel/Kconfig.preempt
config HZ
int
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
ARCH_S5PV210 || ARCH_EXYNOS4
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
......@@ -2028,7 +2016,7 @@ menu "Power management options"
source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE
depends on !ARCH_S5P64X0 && !ARCH_S5P6442 && !ARCH_S5PC100
depends on !ARCH_S5P64X0 && !ARCH_S5PC100
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
def_bool y
......
arch/arm/Makefile
View file @ 586893eb
......@@ -176,7 +176,6 @@ machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c24
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5P6442) := s5p6442
machine-$(CONFIG_ARCH_S5PC100) := s5pc100
machine-$(CONFIG_ARCH_S5PV210) := s5pv210
machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
......
arch/arm/common/Kconfig
View file @ 586893eb
......@@ -7,7 +7,7 @@ config ARM_VIC
config ARM_VIC_NR
int
default 4 if ARCH_S5PV210
default 3 if ARCH_S5P6442 || ARCH_S5PC100
default 3 if ARCH_S5PC100
default 2
depends on ARM_VIC
help
......
arch/arm/configs/exynos4_defconfig
View file @ 586893eb
......@@ -8,7 +8,9 @@ CONFIG_ARCH_EXYNOS4=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDKC210=y
CONFIG_MACH_SMDKV310=y
CONFIG_MACH_ARMLEX4210=y
CONFIG_MACH_UNIVERSAL_C210=y
CONFIG_MACH_NURI=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
......
arch/arm/configs/s5p6442_defconfig deleted 100644 → 0
View file @ 014322da
CONFIG_EXPERIMENTAL=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_S5P6442=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDK6442=y
CONFIG_CPU_32v6K=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
CONFIG_FPE_NWFPE=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
# CONFIG_MISC_DEVICES is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_HW_RANDOM=y
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_INOTIFY=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_S3C_UART=1
CONFIG_CRC_CCITT=y
arch/arm/mach-exynos4/Kconfig
View file @ 586893eb
......@@ -169,9 +169,11 @@ config MACH_NURI
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
select S3C_DEV_I2C3
select S3C_DEV_I2C5
select S5P_DEV_USB_EHCI
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
select SAMSUNG_DEV_PWM
......
arch/arm/mach-exynos4/Makefile
View file @ 586893eb
......@@ -16,6 +16,7 @@ obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
......
arch/arm/mach-exynos4/cpuidle.c 0 → 100644
View file @ 586893eb
/* linux/arch/arm/mach-exynos4/cpuidle.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/cpuidle.h>
#include <linux/io.h>
#include <asm/proc-fns.h>
static int exynos4_enter_idle(struct cpuidle_device *dev,
struct cpuidle_state *state);
static struct cpuidle_state exynos4_cpuidle_set[] = {
[0] = {
.enter = exynos4_enter_idle,
.exit_latency = 1,
.target_residency = 100000,
.flags = CPUIDLE_FLAG_TIME_VALID,
.name = "IDLE",
.desc = "ARM clock gating(WFI)",
},
};
static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
static struct cpuidle_driver exynos4_idle_driver = {
.name = "exynos4_idle",
.owner = THIS_MODULE,
};
static int exynos4_enter_idle(struct cpuidle_device *dev,
struct cpuidle_state *state)
{
struct timeval before, after;
int idle_time;
local_irq_disable();
do_gettimeofday(&before);
cpu_do_idle();
do_gettimeofday(&after);
local_irq_enable();
idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
(after.tv_usec - before.tv_usec);
return idle_time;
}
static int __init exynos4_init_cpuidle(void)
{
int i, max_cpuidle_state, cpu_id;
struct cpuidle_device *device;
cpuidle_register_driver(&exynos4_idle_driver);
for_each_cpu(cpu_id, cpu_online_mask) {
device = &per_cpu(exynos4_cpuidle_device, cpu_id);
device->cpu = cpu_id;
device->state_count = (sizeof(exynos4_cpuidle_set) /
sizeof(struct cpuidle_state));
max_cpuidle_state = device->state_count;
for (i = 0; i < max_cpuidle_state; i++) {
memcpy(&device->states[i], &exynos4_cpuidle_set[i],
sizeof(struct cpuidle_state));
}
if (cpuidle_register_device(device)) {
printk(KERN_ERR "CPUidle register device failed\n,");
return -EIO;
}
}
return 0;
}
device_initcall(exynos4_init_cpuidle);
arch/arm/mach-exynos4/mach-nuri.c
View file @ 586893eb
......@@ -12,6 +12,7 @@
#include <linux/serial_core.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/i2c/atmel_mxt_ts.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
#include <linux/regulator/machine.h>
......@@ -32,6 +33,8 @@
#include <plat/sdhci.h>
#include <plat/ehci.h>
#include <plat/clock.h>
#include <plat/gpio-cfg.h>
#include <plat/iic.h>
#include <mach/map.h>
......@@ -259,6 +262,88 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
/* Gyro, To be updated */
};
/* TSP */
static u8 mxt_init_vals[] = {
/* MXT_GEN_COMMAND(6) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* MXT_GEN_POWER(7) */
0x20, 0xff, 0x32,
/* MXT_GEN_ACQUIRE(8) */
0x0a, 0x00, 0x05, 0x00, 0x00, 0x00, 0x09, 0x23,
/* MXT_TOUCH_MULTI(9) */
0x00, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00,
0x00, 0x01, 0x01, 0x0e, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00,
/* MXT_TOUCH_KEYARRAY(15) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
0x00,
/* MXT_SPT_GPIOPWM(19) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* MXT_PROCI_GRIPFACE(20) */
0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x28, 0x04,
0x0f, 0x0a,
/* MXT_PROCG_NOISE(22) */
0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x23, 0x00,
0x00, 0x05, 0x0f, 0x19, 0x23, 0x2d, 0x03,
/* MXT_TOUCH_PROXIMITY(23) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
/* MXT_PROCI_ONETOUCH(24) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* MXT_SPT_SELFTEST(25) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
/* MXT_PROCI_TWOTOUCH(27) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* MXT_SPT_CTECONFIG(28) */
0x00, 0x00, 0x02, 0x08, 0x10, 0x00,
};
static struct mxt_platform_data mxt_platform_data = {
.config = mxt_init_vals,
.config_length = ARRAY_SIZE(mxt_init_vals),
.x_line = 18,
.y_line = 11,
.x_size = 1024,
.y_size = 600,
.blen = 0x1,
.threshold = 0x28,
.voltage = 2800000, /* 2.8V */
.orient = MXT_DIAGONAL_COUNTER,
.irqflags = IRQF_TRIGGER_FALLING,
};
static struct s3c2410_platform_i2c i2c3_data __initdata = {
.flags = 0,
.bus_num = 3,
.slave_addr = 0x10,
.frequency = 400 * 1000,
.sda_delay = 100,
};
static struct i2c_board_info i2c3_devs[] __initdata = {
{
I2C_BOARD_INFO("atmel_mxt_ts", 0x4a),
.platform_data = &mxt_platform_data,
.irq = IRQ_EINT(4),
},
};
static void __init nuri_tsp_init(void)
{
int gpio;
/* TOUCH_INT: XEINT_4 */
gpio = EXYNOS4_GPX0(4);
gpio_request(gpio, "TOUCH_INT");
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
}
/* GPIO I2C 5 (PMIC) */
static struct i2c_board_info i2c5_devs[] __initdata = {
/* max8997, To be updated */
......@@ -283,6 +368,7 @@ static struct platform_device *nuri_devices[] __initdata = {
&s3c_device_wdt,
&s3c_device_timer[0],
&s5p_device_ehci,
&s3c_device_i2c3,
/* NURI Devices */
&nuri_gpio_keys,
......@@ -300,8 +386,11 @@ static void __init nuri_map_io(void)
static void __init nuri_machine_init(void)
{
nuri_sdhci_init();
nuri_tsp_init();
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
s3c_i2c3_set_platdata(&i2c3_data);
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
nuri_ehci_init();
......
arch/arm/mach-s3c64xx/dev-spi.c
View file @ 586893eb
......@@ -16,7 +16,6 @@
#include <mach/dma.h>
#include <mach/map.h>
#include <mach/gpio-bank-c.h>
#include <mach/spi-clocks.h>
#include <mach/irqs.h>
......@@ -40,23 +39,15 @@ static char *spi_src_clks[] = {
*/
static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0);
s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO);
s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO);
s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP);
base = S3C64XX_GPC(0);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1);
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1);
s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1);
s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP);
base = S3C64XX_GPC(4);
break;
default:
......@@ -64,6 +55,9 @@ static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
return -EINVAL;
}
s3c_gpio_cfgall_range(base, 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
return 0;
}
......
arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank A register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00)
#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04)
#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08)
#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c)
#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10)
#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0)
#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0)
#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4)
#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4)
#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8)
#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8)
#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12)
#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12)
#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16)
#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16)
#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20)
#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20)
#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24)
#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24)
#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28)
#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank B register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00)
#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04)
#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08)
#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c)
#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10)
#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0)
#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0)
#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0)
#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0)
#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0)
#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4)
#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4)
#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4)
#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4)
#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4)
#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8)
#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8)
#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8)
#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8)
#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8)
#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8)
#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12)
#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12)
#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12)
#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12)
#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12)
#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16)
#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16)
#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16)
#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16)
#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20)
#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20)
#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24)
#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank C register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00)
#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04)
#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08)
#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c)
#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10)
#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0)
#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0)
#define S3C64XX_GPC1_SPI_CLKO (0x02 << 4)
#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4)
#define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8)
#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8)
#define S3C64XX_GPC3_SPI_nCSO (0x02 << 12)
#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12)
#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16)
#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16)
#define S3C64XX_GPC4_I2S_V40_DO0 (0x05 << 16)
#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16)
#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20)
#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20)
#define S3C64XX_GPC5_I2S_V40_DO1 (0x05 << 20)
#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20)
#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24)
#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24)
#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28)
#define S3C64XX_GPC7_I2S_V40_DO2 (0x05 << 28)
#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank D register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00)
#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04)
#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08)
#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c)
#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10)
#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0)
#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0)
#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0)
#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0)
#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4)
#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4)
#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4)
#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4)
#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8)
#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8)
#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8)
#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8)
#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12)
#define S3C64XX_GPD3_I2S0_DI (0x03 << 12)
#define S3C64XX_GPD3_AC97_SDI (0x04 << 12)
#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12)
#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16)
#define S3C64XX_GPD4_I2S0_D0 (0x03 << 16)
#define S3C64XX_GPD4_AC97_SDO (0x04 << 16)
#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank E register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00)
#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04)
#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08)
#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c)
#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10)
#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0)
#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0)
#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0)
#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4)
#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4)
#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4)
#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8)
#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8)
#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8)
#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12)
#define S3C64XX_GPE3_I2S1_DI (0x03 << 12)
#define S3C64XX_GPE3_AC97_SDI (0x04 << 12)
#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16)
#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16)
#define S3C64XX_GPE4_AC97_SDO (0x04 << 16)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank F register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00)
#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04)
#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08)
#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c)
#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10)
#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0)
#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0)
#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2)
#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2)
#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4)
#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4)
#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6)
#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6)
#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8)
#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8)
#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10)
#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10)
#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12)
#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12)
#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14)
#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14)
#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16)
#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16)
#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18)
#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18)
#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20)
#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20)
#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22)
#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22)
#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24)
#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24)
#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26)
#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26)
#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28)
#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28)
#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank G register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00)
#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04)
#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08)
#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c)
#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10)
#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0)
#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0)
#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4)
#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4)
#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8)
#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8)
#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12)
#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12)
#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16)
#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16)
#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20)
#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank H register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00)
#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04)
#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08)
#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c)
#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10)
#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14)
#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0)
#define S3C64XX_GPH0_KP_COL0 (0x04 << 0)
#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0)
#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4)
#define S3C64XX_GPH1_KP_COL1 (0x04 << 4)
#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4)
#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8)
#define S3C64XX_GPH2_KP_COL2 (0x04 << 8)
#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8)
#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12)
#define S3C64XX_GPH3_KP_COL3 (0x04 << 12)
#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12)
#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16)
#define S3C64XX_GPH4_KP_COL4 (0x04 << 16)
#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16)
#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20)
#define S3C64XX_GPH5_KP_COL5 (0x04 << 20)
#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20)
#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24)
#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24)
#define S3C64XX_GPH6_KP_COL6 (0x04 << 24)
#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24)
#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24)
#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24)
#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28)
#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28)
#define S3C64XX_GPH7_KP_COL7 (0x04 << 28)
#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28)
#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 0)
#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 0)
#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 0)
#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 0)
#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 0)
#define S3C64XX_GPH9_OUTPUT (0x01 << 4)
#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 4)
#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 4)
#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 4)
#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 4)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank I register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00)
#define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04)
#define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08)
#define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c)
#define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10)
#define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPI0_VD0 (0x02 << 0)
#define S3C64XX_GPI1_VD1 (0x02 << 2)
#define S3C64XX_GPI2_VD2 (0x02 << 4)
#define S3C64XX_GPI3_VD3 (0x02 << 6)
#define S3C64XX_GPI4_VD4 (0x02 << 8)
#define S3C64XX_GPI5_VD5 (0x02 << 10)
#define S3C64XX_GPI6_VD6 (0x02 << 12)
#define S3C64XX_GPI7_VD7 (0x02 << 14)
#define S3C64XX_GPI8_VD8 (0x02 << 16)
#define S3C64XX_GPI9_VD9 (0x02 << 18)
#define S3C64XX_GPI10_VD10 (0x02 << 20)
#define S3C64XX_GPI11_VD11 (0x02 << 22)
#define S3C64XX_GPI12_VD12 (0x02 << 24)
#define S3C64XX_GPI13_VD13 (0x02 << 26)
#define S3C64XX_GPI14_VD14 (0x02 << 28)
#define S3C64XX_GPI15_VD15 (0x02 << 30)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank J register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00)
#define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04)
#define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08)
#define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c)
#define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10)
#define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPJ0_VD16 (0x02 << 0)
#define S3C64XX_GPJ1_VD17 (0x02 << 2)
#define S3C64XX_GPJ2_VD18 (0x02 << 4)
#define S3C64XX_GPJ3_VD19 (0x02 << 6)
#define S3C64XX_GPJ4_VD20 (0x02 << 8)
#define S3C64XX_GPJ5_VD21 (0x02 << 10)
#define S3C64XX_GPJ6_VD22 (0x02 << 12)
#define S3C64XX_GPJ7_VD23 (0x02 << 14)
#define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16)
#define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18)
#define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20)
#define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank N register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
#define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08)
#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPN0_EINT0 (0x02 << 0)
#define S3C64XX_GPN0_KP_ROW0 (0x03 << 0)
#define S3C64XX_GPN1_EINT1 (0x02 << 2)
#define S3C64XX_GPN1_KP_ROW1 (0x03 << 2)
#define S3C64XX_GPN2_EINT2 (0x02 << 4)
#define S3C64XX_GPN2_KP_ROW2 (0x03 << 4)
#define S3C64XX_GPN3_EINT3 (0x02 << 6)
#define S3C64XX_GPN3_KP_ROW3 (0x03 << 6)
#define S3C64XX_GPN4_EINT4 (0x02 << 8)
#define S3C64XX_GPN4_KP_ROW4 (0x03 << 8)
#define S3C64XX_GPN5_EINT5 (0x02 << 10)
#define S3C64XX_GPN5_KP_ROW5 (0x03 << 10)
#define S3C64XX_GPN6_EINT6 (0x02 << 12)
#define S3C64XX_GPN6_KP_ROW6 (0x03 << 12)
#define S3C64XX_GPN7_EINT7 (0x02 << 14)
#define S3C64XX_GPN7_KP_ROW7 (0x03 << 14)
#define S3C64XX_GPN8_EINT8 (0x02 << 16)
#define S3C64XX_GPN9_EINT9 (0x02 << 18)
#define S3C64XX_GPN10_EINT10 (0x02 << 20)
#define S3C64XX_GPN11_EINT11 (0x02 << 22)
#define S3C64XX_GPN12_EINT12 (0x02 << 24)
#define S3C64XX_GPN13_EINT13 (0x02 << 26)
#define S3C64XX_GPN14_EINT14 (0x02 << 28)
#define S3C64XX_GPN15_EINT15 (0x02 << 30)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank O register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00)
#define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04)
#define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08)
#define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c)
#define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10)
#define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0)
#define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0)
#define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2)
#define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2)
#define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4)
#define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4)
#define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6)
#define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6)
#define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8)
#define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10)
#define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12)
#define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12)
#define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14)
#define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14)
#define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16)
#define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16)
#define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18)
#define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18)
#define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20)
#define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20)
#define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22)
#define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22)
#define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24)
#define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24)
#define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26)
#define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26)
#define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28)
#define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28)
#define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30)
#define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank P register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00)
#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04)
#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08)
#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c)
#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10)
#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0)
#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0)
#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2)
#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2)
#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4)
#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4)
#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6)
#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6)
#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8)
#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8)
#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10)
#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10)
#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12)
#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12)
#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14)
#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14)
#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16)
#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16)
#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18)
#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18)
#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20)
#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20)
#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22)
#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22)
#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24)
#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24)
#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26)
#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26)
#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28)
#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28)
arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank Q register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00)
#define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04)
#define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08)
#define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c)
#define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10)
#define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0)
#define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0)
#define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2)
#define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2)
#define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4)
#define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6)
#define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8)
#define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10)
#define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12)
#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14)
#define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14)
#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16)
#define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16)
arch/arm/mach-s3c64xx/mach-smdk6410.c
View file @ 586893eb
......@@ -50,7 +50,6 @@
#include <mach/hardware.h>
#include <mach/regs-fb.h>
#include <mach/map.h>
#include <mach/gpio-bank-f.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
......
arch/arm/mach-s3c64xx/pm.c
View file @ 586893eb
......@@ -30,26 +30,18 @@
#include <mach/regs-gpio-memport.h>
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
#include <mach/gpio-bank-n.h>
void s3c_pm_debug_smdkled(u32 set, u32 clear)
{
unsigned long flags;
u32 reg;
int i;
local_irq_save(flags);
reg = __raw_readl(S3C64XX_GPNCON);
reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) |
S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15));
reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) |
S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15);
__raw_writel(reg, S3C64XX_GPNCON);
reg = __raw_readl(S3C64XX_GPNDAT);
reg &= ~(clear << 12);
reg |= set << 12;
__raw_writel(reg, S3C64XX_GPNDAT);
for (i = 0; i < 4; i++) {
if (clear & (1 << i))
gpio_set_value(S3C64XX_GPN(12 + i), 0);
if (set & (1 << i))
gpio_set_value(S3C64XX_GPN(12 + i), 1);
}
local_irq_restore(flags);
}
#endif
......@@ -187,6 +179,18 @@ static int s3c64xx_pm_init(void)
pm_cpu_prep = s3c64xx_pm_prepare;
pm_cpu_sleep = s3c64xx_cpu_suspend;
pm_uart_udivslot = 1;
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
gpio_direction_output(S3C64XX_GPN(12), 0);
gpio_direction_output(S3C64XX_GPN(13), 0);
gpio_direction_output(S3C64XX_GPN(14), 0);
gpio_direction_output(S3C64XX_GPN(15), 0);
#endif
return 0;
}
......
arch/arm/mach-s3c64xx/setup-i2c0.c
View file @ 586893eb
......@@ -18,14 +18,11 @@
struct platform_device; /* don't need the contents */
#include <mach/gpio-bank-b.h>
#include <plat/iic.h>
#include <plat/gpio-cfg.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgall_range(S3C64XX_GPB(5), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
arch/arm/mach-s3c64xx/setup-i2c1.c
View file @ 586893eb
......@@ -18,14 +18,11 @@
struct platform_device; /* don't need the contents */
#include <mach/gpio-bank-b.h>
#include <plat/iic.h>
#include <plat/gpio-cfg.h>
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1);
s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1);
s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP);
s3c_gpio_cfgall_range(S3C64XX_GPB(2), 2,
S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
}
arch/arm/mach-s3c64xx/sleep.S
View file @ 586893eb
......@@ -20,7 +20,6 @@
#define S3C64XX_VA_GPIO (0x0)
#include <mach/regs-gpio.h>
#include <mach/gpio-bank-n.h>
#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
......@@ -68,6 +67,13 @@ ENTRY(s3c_cpu_resume)
ldr r2, =LL_UART /* for debug */
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
/* Initialise the GPIO state if we are debugging via the SMDK LEDs,
* as the uboot version supplied resets these to inputs during the
* resume checks.
......
arch/arm/mach-s5p6442/Kconfig deleted 100644 → 0
View file @ 014322da
# arch/arm/mach-s5p6442/Kconfig
#
# Copyright (c) 2010 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
# Configuration options for the S5P6442
if ARCH_S5P6442
config CPU_S5P6442
bool
select S3C_PL330_DMA
help
Enable S5P6442 CPU support
config MACH_SMDK6442
bool "SMDK6442"
select CPU_S5P6442
select S3C_DEV_WDT
help
Machine support for Samsung SMDK6442
endif
arch/arm/mach-s5p6442/Makefile deleted 100644 → 0
View file @ 014322da
# arch/arm/mach-s5p6442/Makefile
#
# Copyright (c) 2010 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S5P6442 system
obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o dma.o
obj-$(CONFIG_CPU_S5P6442) += setup-i2c0.o
# machine support
obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o
# device support
obj-y += dev-audio.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
arch/arm/mach-s5p6442/Makefile.boot deleted 100644 → 0
View file @ 014322da
zreladdr-y := 0x20008000
params_phys-y := 0x20000100
arch/arm/mach-s5p6442/clock.c deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/clock.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/map.h>
#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p6442.h>
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
};
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
};
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
};
/* Possible clock sources for ARM Mux */
static struct clk *clk_src_arm_list[] = {
[1] = &clk_mout_apll.clk,
[2] = &clk_mout_mpll.clk,
};
static struct clksrc_sources clk_src_arm = {
.sources = clk_src_arm_list,
.nr_sources = ARRAY_SIZE(clk_src_arm_list),
};
static struct clksrc_clk clk_mout_arm = {
.clk = {
.name = "mout_arm",
.id = -1,
},
.sources = &clk_src_arm,
.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
};
static struct clk clk_dout_a2m = {
.name = "dout_a2m",
.id = -1,
.parent = &clk_mout_apll.clk,
};
/* Possible clock sources for D0 Mux */
static struct clk *clk_src_d0_list[] = {
[1] = &clk_mout_mpll.clk,
[2] = &clk_dout_a2m,
};
static struct clksrc_sources clk_src_d0 = {
.sources = clk_src_d0_list,
.nr_sources = ARRAY_SIZE(clk_src_d0_list),
};
static struct clksrc_clk clk_mout_d0 = {
.clk = {
.name = "mout_d0",
.id = -1,
},
.sources = &clk_src_d0,
.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 20, .size = 3 },
};
static struct clk clk_dout_apll = {
.name = "dout_apll",
.id = -1,
.parent = &clk_mout_arm.clk,
};
/* Possible clock sources for D0SYNC Mux */
static struct clk *clk_src_d0sync_list[] = {
[1] = &clk_mout_d0.clk,
[2] = &clk_dout_apll,
};
static struct clksrc_sources clk_src_d0sync = {
.sources = clk_src_d0sync_list,
.nr_sources = ARRAY_SIZE(clk_src_d0sync_list),
};
static struct clksrc_clk clk_mout_d0sync = {
.clk = {
.name = "mout_d0sync",
.id = -1,
},
.sources = &clk_src_d0sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
};
/* Possible clock sources for D1 Mux */
static struct clk *clk_src_d1_list[] = {
[1] = &clk_mout_mpll.clk,
[2] = &clk_dout_a2m,
};
static struct clksrc_sources clk_src_d1 = {
.sources = clk_src_d1_list,
.nr_sources = ARRAY_SIZE(clk_src_d1_list),
};
static struct clksrc_clk clk_mout_d1 = {
.clk = {
.name = "mout_d1",
.id = -1,
},
.sources = &clk_src_d1,
.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 24, .size = 3 },
};
/* Possible clock sources for D1SYNC Mux */
static struct clk *clk_src_d1sync_list[] = {
[1] = &clk_mout_d1.clk,
[2] = &clk_dout_apll,
};
static struct clksrc_sources clk_src_d1sync = {
.sources = clk_src_d1sync_list,
.nr_sources = ARRAY_SIZE(clk_src_d1sync_list),
};
static struct clksrc_clk clk_mout_d1sync = {
.clk = {
.name = "mout_d1sync",
.id = -1,
},
.sources = &clk_src_d1sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
};
static struct clk clk_hclkd0 = {
.name = "hclkd0",
.id = -1,
.parent = &clk_mout_d0sync.clk,
};
static struct clk clk_hclkd1 = {
.name = "hclkd1",
.id = -1,
.parent = &clk_mout_d1sync.clk,
};
static struct clk clk_pclkd0 = {
.name = "pclkd0",
.id = -1,
.parent = &clk_hclkd0,
};
static struct clk clk_pclkd1 = {
.name = "pclkd1",
.id = -1,
.parent = &clk_hclkd1,
};
int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
}
int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
}
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "dout_a2m",
.id = -1,
.parent = &clk_mout_apll.clk,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
}, {
.clk = {
.name = "dout_apll",
.id = -1,
.parent = &clk_mout_arm.clk,
},
.sources = &clk_src_arm,
.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
}, {
.clk = {
.name = "hclkd1",
.id = -1,
.parent = &clk_mout_d1sync.clk,
},
.sources = &clk_src_d1sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
}, {
.clk = {
.name = "hclkd0",
.id = -1,
.parent = &clk_mout_d0sync.clk,
},
.sources = &clk_src_d0sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "pclkd0",
.id = -1,
.parent = &clk_hclkd0,
},
.sources = &clk_src_d0sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
}, {
.clk = {
.name = "pclkd1",
.id = -1,
.parent = &clk_hclkd1,
},
.sources = &clk_src_d1sync,
.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
}
};
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
&clk_mout_apll,
&clk_mout_mpll,
&clk_mout_epll,
&clk_mout_arm,
&clk_mout_d0,
&clk_mout_d0sync,
&clk_mout_d1,
&clk_mout_d1sync,
};
void __init_or_cpufreq s5p6442_setup_clocks(void)
{
struct clk *pclkd0_clk;
struct clk *pclkd1_clk;
unsigned long xtal;
unsigned long arm;
unsigned long hclkd0 = 0;
unsigned long hclkd1 = 0;
unsigned long pclkd0 = 0;
unsigned long pclkd1 = 0;
unsigned long apll;
unsigned long mpll;
unsigned long epll;
unsigned int ptr;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
xtal = clk_get_rate(&clk_xtal);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld",
apll, mpll, epll);
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c_set_clksrc(init_parents[ptr], true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
arm = clk_get_rate(&clk_dout_apll);
hclkd0 = clk_get_rate(&clk_hclkd0);
hclkd1 = clk_get_rate(&clk_hclkd1);
pclkd0_clk = clk_get(NULL, "pclkd0");
BUG_ON(IS_ERR(pclkd0_clk));
pclkd0 = clk_get_rate(pclkd0_clk);
clk_put(pclkd0_clk);
pclkd1_clk = clk_get(NULL, "pclkd1");
BUG_ON(IS_ERR(pclkd1_clk));
pclkd1 = clk_get_rate(pclkd1_clk);
clk_put(pclkd1_clk);
printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n",
hclkd0, hclkd1, pclkd0, pclkd1);
/* For backward compatibility */
clk_f.rate = arm;
clk_h.rate = hclkd1;
clk_p.rate = pclkd1;
clk_pclkd0.rate = pclkd0;
clk_pclkd1.rate = pclkd1;
}
static struct clk init_clocks_off[] = {
{
.name = "pdma",
.id = -1,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip0_ctrl,
.ctrlbit = (1 << 3),
},
};
static struct clk init_clocks[] = {
{
.name = "systimer",
.id = -1,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "uart",
.id = 0,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "uart",
.id = 1,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1<<18),
}, {
.name = "uart",
.id = 2,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1<<19),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "timers",
.id = -1,
.parent = &clk_pclkd1,
.enable = s5p6442_clk_ip3_ctrl,
.ctrlbit = (1<<23),
},
};
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_epll,
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
&clk_mout_epll.clk,
&clk_mout_d0.clk,
&clk_mout_d0sync.clk,
&clk_mout_d1.clk,
&clk_mout_d1sync.clk,
&clk_hclkd0,
&clk_pclkd0,
&clk_hclkd1,
&clk_pclkd1,
};
void __init s5p6442_register_clocks(void)
{
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_pwmclk_init();
}
arch/arm/mach-s5p6442/cpu.c deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/cpu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/proc-fns.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <plat/regs-serial.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/s5p6442.h>
/* Initial IO mappings */
static struct map_desc s5p6442_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(S5P6442_PA_SYSTIMER),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO,
.pfn = __phys_to_pfn(S5P6442_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC0,
.pfn = __phys_to_pfn(S5P6442_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC1,
.pfn = __phys_to_pfn(S5P6442_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC2,
.pfn = __phys_to_pfn(S5P6442_PA_VIC2),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
}
};
static void s5p6442_idle(void)
{
if (!need_resched())
cpu_do_idle();
local_irq_enable();
}
/*
* s5p6442_map_io
*
* register the standard cpu IO areas
*/
void __init s5p6442_map_io(void)
{
iotable_init(s5p6442_iodesc, ARRAY_SIZE(s5p6442_iodesc));
}
void __init s5p6442_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5p6442_register_clocks();
s5p6442_setup_clocks();
}
void __init s5p6442_init_irq(void)
{
/* S5P6442 supports 3 VIC */
u32 vic[3];
/* VIC0, VIC1, and VIC2: some interrupt reserved */
vic[0] = 0x7fefffff;
vic[1] = 0X7f389c81;
vic[2] = 0X1bbbcfff;
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
struct sysdev_class s5p6442_sysclass = {
.name = "s5p6442-core",
};
static struct sys_device s5p6442_sysdev = {
.cls = &s5p6442_sysclass,
};
static int __init s5p6442_core_init(void)
{
return sysdev_class_register(&s5p6442_sysclass);
}
core_initcall(s5p6442_core_init);
int __init s5p6442_init(void)
{
printk(KERN_INFO "S5P6442: Initializing architecture\n");
/* set idle function */
pm_idle = s5p6442_idle;
return sysdev_register(&s5p6442_sysdev);
}
arch/arm/mach-s5p6442/dev-audio.c deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/dev-audio.c
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/audio.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
static int s5p6442_cfg_i2s(struct platform_device *pdev)
{
unsigned int base;
/* configure GPIO for i2s port */
switch (pdev->id) {
case 1:
base = S5P6442_GPC1(0);
break;
case 0:
base = S5P6442_GPC0(0);
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
return 0;
}
static const char *rclksrc_v35[] = {
[0] = "busclk",
[1] = "i2sclk",
};
static struct s3c_audio_pdata i2sv35_pdata = {
.cfg_gpio = s5p6442_cfg_i2s,
.type = {
.i2s = {
.quirks = QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR,
.src_clk = rclksrc_v35,
},
},
};
static struct resource s5p6442_iis0_resource[] = {
[0] = {
.start = S5P6442_PA_I2S0,
.end = S5P6442_PA_I2S0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S0_TX,
.end = DMACH_I2S0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S0_RX,
.end = DMACH_I2S0_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DMACH_I2S0S_TX,
.end = DMACH_I2S0S_TX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_iis0 = {
.name = "samsung-i2s",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6442_iis0_resource),
.resource = s5p6442_iis0_resource,
.dev = {
.platform_data = &i2sv35_pdata,
},
};
static const char *rclksrc_v3[] = {
[0] = "iis",
[1] = "sclk_audio",
};
static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = s5p6442_cfg_i2s,
.type = {
.i2s = {
.src_clk = rclksrc_v3,
},
},
};
static struct resource s5p6442_iis1_resource[] = {
[0] = {
.start = S5P6442_PA_I2S1,
.end = S5P6442_PA_I2S1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S1_TX,
.end = DMACH_I2S1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S1_RX,
.end = DMACH_I2S1_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_iis1 = {
.name = "samsung-i2s",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6442_iis1_resource),
.resource = s5p6442_iis1_resource,
.dev = {
.platform_data = &i2sv3_pdata,
},
};
/* PCM Controller platform_devices */
static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S5P6442_GPC0(0);
break;
case 1:
base = S5P6442_GPC1(0);
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0;
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5p6442_pcm_cfg_gpio,
};
static struct resource s5p6442_pcm0_resource[] = {
[0] = {
.start = S5P6442_PA_PCM0,
.end = S5P6442_PA_PCM0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM0_TX,
.end = DMACH_PCM0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM0_RX,
.end = DMACH_PCM0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_pcm0 = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6442_pcm0_resource),
.resource = s5p6442_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5p6442_pcm1_resource[] = {
[0] = {
.start = S5P6442_PA_PCM1,
.end = S5P6442_PA_PCM1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM1_TX,
.end = DMACH_PCM1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM1_RX,
.end = DMACH_PCM1_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_pcm1 = {
.name = "samsung-pcm",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6442_pcm1_resource),
.resource = s5p6442_pcm1_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
arch/arm/mach-s5p6442/dev-spi.c deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/dev-spi.c
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <mach/dma.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/spi-clocks.h>
#include <plat/s3c64xx-spi.h>
#include <plat/gpio-cfg.h>
static char *spi_src_clks[] = {
[S5P6442_SPI_SRCCLK_PCLK] = "pclk",
[S5P6442_SPI_SRCCLK_SCLK] = "spi_epll",
};
/* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the CS.
* The emulated CS is toggled by board specific mechanism, as it can
* be either some immediate GPIO or some signal out of some other
* chip in between ... or some yet another way.
* We simply do not assume anything about CS.
*/
static int s5p6442_spi_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP);
s3c_gpio_cfgall_range(S5P6442_GPB(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
break;
default:
dev_err(&pdev->dev, "Invalid SPI Controller number!");
return -EINVAL;
}
return 0;
}
static struct resource s5p6442_spi0_resource[] = {
[0] = {
.start = S5P6442_PA_SPI,
.end = S5P6442_PA_SPI + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_SPI0_TX,
.end = DMACH_SPI0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_SPI0_RX,
.end = DMACH_SPI0_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = IRQ_SPI0,
.end = IRQ_SPI0,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c64xx_spi_info s5p6442_spi0_pdata = {
.cfg_gpio = s5p6442_spi_cfg_gpio,
.fifo_lvl_mask = 0x1ff,
.rx_lvl_offset = 15,
};
static u64 spi_dmamask = DMA_BIT_MASK(32);
struct platform_device s5p6442_device_spi = {
.name = "s3c64xx-spi",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6442_spi0_resource),
.resource = s5p6442_spi0_resource,
.dev = {
.dma_mask = &spi_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6442_spi0_pdata,
},
};
void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
{
struct s3c64xx_spi_info *pd;
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0
|| src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) {
printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
return;
}
switch (cntrlr) {
case 0:
pd = &s5p6442_spi0_pdata;
break;
default:
printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
__func__, cntrlr);
return;
}
pd->num_cs = num_cs;
pd->src_clk_nr = src_clk_nr;
pd->src_clk_name = spi_src_clks[src_clk_nr];
}
arch/arm/mach-s5p6442/dma.c deleted 100644 → 0
View file @ 014322da
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/s3c-pl330-pdata.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5p6442_pdma_resource[] = {
[0] = {
.start = S5P6442_PA_PDMA,
.end = S5P6442_PA_PDMA + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PDMA,
.end = IRQ_PDMA,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_pl330_platdata s5p6442_pdma_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_MAX,
[7] = DMACH_MAX,
[8] = DMACH_MAX,
[9] = DMACH_I2S0_RX,
[10] = DMACH_I2S0_TX,
[11] = DMACH_I2S0S_TX,
[12] = DMACH_I2S1_RX,
[13] = DMACH_I2S1_TX,
[14] = DMACH_MAX,
[15] = DMACH_MAX,
[16] = DMACH_SPI0_RX,
[17] = DMACH_SPI0_TX,
[18] = DMACH_MAX,
[19] = DMACH_MAX,
[20] = DMACH_PCM0_RX,
[21] = DMACH_PCM0_TX,
[22] = DMACH_PCM1_RX,
[23] = DMACH_PCM1_TX,
[24] = DMACH_MAX,
[25] = DMACH_MAX,
[26] = DMACH_MAX,
[27] = DMACH_MSM_REQ0,
[28] = DMACH_MSM_REQ1,
[29] = DMACH_MSM_REQ2,
[30] = DMACH_MSM_REQ3,
[31] = DMACH_MAX,
},
};
static struct platform_device s5p6442_device_pdma = {
.name = "s3c-pl330",
.id = -1,
.num_resources = ARRAY_SIZE(s5p6442_pdma_resource),
.resource = s5p6442_pdma_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6442_pdma_pdata,
},
};
static struct platform_device *s5p6442_dmacs[] __initdata = {
&s5p6442_device_pdma,
};
static int __init s5p6442_dma_init(void)
{
platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs));
return 0;
}
arch_initcall(s5p6442_dma_init);
arch/arm/mach-s5p6442/include/mach/debug-macro.S deleted 100644 → 0
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/* linux/arch/arm/mach-s5p6442/include/mach/debug-macro.S
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <mach/map.h>
#include <plat/regs-serial.h>
.macro addruart, rp, rv
ldr \rp, = S3C_PA_UART
ldr \rv, = S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
#endif
.endm
#define fifo_full fifo_full_s5pv210
#define fifo_level fifo_level_s5pv210
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <plat/debug-macro.S>
arch/arm/mach-s5p6442/include/mach/dma.h deleted 100644 → 0
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/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common S3C DMA API driver for PL330 */
#include <plat/s3c-dma-pl330.h>
#endif /* __MACH_DMA_H */
arch/arm/mach-s5p6442/include/mach/entry-macro.S deleted 100644 → 0
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/* linux/arch/arm/mach-s5p6442/include/mach/entry-macro.S
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Low-level IRQ helper macros for the Samsung S5P6442
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/hardware/vic.h>
#include <mach/map.h>
#include <plat/irqs.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =VA_VIC0
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ check the vic0
mov \irqnr, # S5P_IRQ_OFFSET + 31
ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
teq \irqstat, #0
@ otherwise try vic1
addeq \tmp, \base, #(VA_VIC1 - VA_VIC0)
addeq \irqnr, \irqnr, #32
ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
teqeq \irqstat, #0
@ otherwise try vic2
addeq \tmp, \base, #(VA_VIC2 - VA_VIC0)
addeq \irqnr, \irqnr, #32
ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
teqeq \irqstat, #0
clzne \irqstat, \irqstat
subne \irqnr, \irqnr, \irqstat
.endm
arch/arm/mach-s5p6442/include/mach/gpio.h deleted 100644 → 0
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/* linux/arch/arm/mach-s5p6442/include/mach/gpio.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* GPIO bank sizes */
#define S5P6442_GPIO_A0_NR (8)
#define S5P6442_GPIO_A1_NR (2)
#define S5P6442_GPIO_B_NR (4)
#define S5P6442_GPIO_C0_NR (5)
#define S5P6442_GPIO_C1_NR (5)
#define S5P6442_GPIO_D0_NR (2)
#define S5P6442_GPIO_D1_NR (6)
#define S5P6442_GPIO_E0_NR (8)
#define S5P6442_GPIO_E1_NR (5)
#define S5P6442_GPIO_F0_NR (8)
#define S5P6442_GPIO_F1_NR (8)
#define S5P6442_GPIO_F2_NR (8)
#define S5P6442_GPIO_F3_NR (6)
#define S5P6442_GPIO_G0_NR (7)
#define S5P6442_GPIO_G1_NR (7)
#define S5P6442_GPIO_G2_NR (7)
#define S5P6442_GPIO_H0_NR (8)
#define S5P6442_GPIO_H1_NR (8)
#define S5P6442_GPIO_H2_NR (8)
#define S5P6442_GPIO_H3_NR (8)
#define S5P6442_GPIO_J0_NR (8)
#define S5P6442_GPIO_J1_NR (6)
#define S5P6442_GPIO_J2_NR (8)
#define S5P6442_GPIO_J3_NR (8)
#define S5P6442_GPIO_J4_NR (5)
/* GPIO bank numbers */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
* space for debugging purposes so that any accidental
* change from one gpio bank to another can be caught.
*/
#define S5P6442_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s5p_gpio_number {
S5P6442_GPIO_A0_START = 0,
S5P6442_GPIO_A1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A0),
S5P6442_GPIO_B_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A1),
S5P6442_GPIO_C0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_B),
S5P6442_GPIO_C1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C0),
S5P6442_GPIO_D0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C1),
S5P6442_GPIO_D1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D0),
S5P6442_GPIO_E0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D1),
S5P6442_GPIO_E1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E0),
S5P6442_GPIO_F0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E1),
S5P6442_GPIO_F1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F0),
S5P6442_GPIO_F2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F1),
S5P6442_GPIO_F3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F2),
S5P6442_GPIO_G0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F3),
S5P6442_GPIO_G1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G0),
S5P6442_GPIO_G2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G1),
S5P6442_GPIO_H0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G2),
S5P6442_GPIO_H1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H0),
S5P6442_GPIO_H2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H1),
S5P6442_GPIO_H3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H2),
S5P6442_GPIO_J0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H3),
S5P6442_GPIO_J1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J0),
S5P6442_GPIO_J2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J1),
S5P6442_GPIO_J3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J2),
S5P6442_GPIO_J4_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J3),
};
/* S5P6442 GPIO number definitions. */
#define S5P6442_GPA0(_nr) (S5P6442_GPIO_A0_START + (_nr))
#define S5P6442_GPA1(_nr) (S5P6442_GPIO_A1_START + (_nr))
#define S5P6442_GPB(_nr) (S5P6442_GPIO_B_START + (_nr))
#define S5P6442_GPC0(_nr) (S5P6442_GPIO_C0_START + (_nr))
#define S5P6442_GPC1(_nr) (S5P6442_GPIO_C1_START + (_nr))
#define S5P6442_GPD0(_nr) (S5P6442_GPIO_D0_START + (_nr))
#define S5P6442_GPD1(_nr) (S5P6442_GPIO_D1_START + (_nr))
#define S5P6442_GPE0(_nr) (S5P6442_GPIO_E0_START + (_nr))
#define S5P6442_GPE1(_nr) (S5P6442_GPIO_E1_START + (_nr))
#define S5P6442_GPF0(_nr) (S5P6442_GPIO_F0_START + (_nr))
#define S5P6442_GPF1(_nr) (S5P6442_GPIO_F1_START + (_nr))
#define S5P6442_GPF2(_nr) (S5P6442_GPIO_F2_START + (_nr))
#define S5P6442_GPF3(_nr) (S5P6442_GPIO_F3_START + (_nr))
#define S5P6442_GPG0(_nr) (S5P6442_GPIO_G0_START + (_nr))
#define S5P6442_GPG1(_nr) (S5P6442_GPIO_G1_START + (_nr))
#define S5P6442_GPG2(_nr) (S5P6442_GPIO_G2_START + (_nr))
#define S5P6442_GPH0(_nr) (S5P6442_GPIO_H0_START + (_nr))
#define S5P6442_GPH1(_nr) (S5P6442_GPIO_H1_START + (_nr))
#define S5P6442_GPH2(_nr) (S5P6442_GPIO_H2_START + (_nr))
#define S5P6442_GPH3(_nr) (S5P6442_GPIO_H3_START + (_nr))
#define S5P6442_GPJ0(_nr) (S5P6442_GPIO_J0_START + (_nr))
#define S5P6442_GPJ1(_nr) (S5P6442_GPIO_J1_START + (_nr))
#define S5P6442_GPJ2(_nr) (S5P6442_GPIO_J2_START + (_nr))
#define S5P6442_GPJ3(_nr) (S5P6442_GPIO_J3_START + (_nr))
#define S5P6442_GPJ4(_nr) (S5P6442_GPIO_J4_START + (_nr))
/* the end of the S5P6442 specific gpios */
#define S5P6442_GPIO_END (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + 1)
#define S3C_GPIO_END S5P6442_GPIO_END
/* define the number of gpios we need to the one after the GPJ4() range */
#define ARCH_NR_GPIOS (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + \
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
#include <asm-generic/gpio.h>
#endif /* __ASM_ARCH_GPIO_H */
arch/arm/mach-s5p6442/include/mach/hardware.h deleted 100644 → 0
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/* linux/arch/arm/mach-s5p6442/include/mach/hardware.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Hardware support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H __FILE__
/* currently nothing here, placeholder */
#endif /* __ASM_ARCH_HARDWARE_H */
arch/arm/mach-s5p6442/include/mach/io.h deleted 100644 → 0
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/* arch/arm/mach-s5p6442/include/mach/io.h
*
* Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
*
* Default IO routines for S5P6442
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
/* No current ISA/PCI bus support. */
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#define IO_SPACE_LIMIT (0xFFFFFFFF)
#endif
arch/arm/mach-s5p6442/include/mach/irqs.h deleted 100644 → 0
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/* linux/arch/arm/mach-s5p6442/include/mach/irqs.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - IRQ definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
#include <plat/irqs.h>
/* VIC0 */
#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
#define IRQ_BATF S5P_IRQ_VIC0(17)
#define IRQ_MDMA S5P_IRQ_VIC0(18)
#define IRQ_PDMA S5P_IRQ_VIC0(19)
#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
#define IRQ_WDT S5P_IRQ_VIC0(27)
#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
/* VIC1 */
#define IRQ_PMU S5P_IRQ_VIC1(0)
#define IRQ_ONENAND S5P_IRQ_VIC1(7)
#define IRQ_UART0 S5P_IRQ_VIC1(10)
#define IRQ_UART1 S5P_IRQ_VIC1(11)
#define IRQ_UART2 S5P_IRQ_VIC1(12)
#define IRQ_SPI0 S5P_IRQ_VIC1(15)
#define IRQ_IIC S5P_IRQ_VIC1(19)
#define IRQ_IIC1 S5P_IRQ_VIC1(20)
#define IRQ_IIC2 S5P_IRQ_VIC1(21)
#define IRQ_OTG S5P_IRQ_VIC1(24)
#define IRQ_MSM S5P_IRQ_VIC1(25)
#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
#define IRQ_COMMRX S5P_IRQ_VIC1(29)
#define IRQ_COMMTX S5P_IRQ_VIC1(30)
/* VIC2 */
#define IRQ_LCD0 S5P_IRQ_VIC2(0)
#define IRQ_LCD1 S5P_IRQ_VIC2(1)
#define IRQ_LCD2 S5P_IRQ_VIC2(2)
#define IRQ_LCD3 S5P_IRQ_VIC2(3)
#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
#define IRQ_JPEG S5P_IRQ_VIC2(8)
#define IRQ_3D S5P_IRQ_VIC2(10)
#define IRQ_Mixer S5P_IRQ_VIC2(11)
#define IRQ_MFC S5P_IRQ_VIC2(14)
#define IRQ_TVENC S5P_IRQ_VIC2(15)
#define IRQ_I2S0 S5P_IRQ_VIC2(16)
#define IRQ_I2S1 S5P_IRQ_VIC2(17)
#define IRQ_RP S5P_IRQ_VIC2(19)
#define IRQ_PCM0 S5P_IRQ_VIC2(20)
#define IRQ_PCM1 S5P_IRQ_VIC2(21)
#define IRQ_ADC S5P_IRQ_VIC2(23)
#define IRQ_PENDN S5P_IRQ_VIC2(24)
#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
#define IRQ_SSS_INT S5P_IRQ_VIC2(27)
#define IRQ_SSS_HASH S5P_IRQ_VIC2(28)
#define IRQ_VIC_END S5P_IRQ_VIC2(31)
#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1)
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE)
/* Set the default NR_IRQS */
#define NR_IRQS (IRQ_EINT(31) + 1)
#endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach-s5p6442/include/mach/map.h deleted 100644 → 0
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/* linux/arch/arm/mach-s5p6442/include/mach/map.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5P6442_PA_SDRAM 0x20000000
#define S5P6442_PA_I2S0 0xC0B00000
#define S5P6442_PA_I2S1 0xF2200000
#define S5P6442_PA_CHIPID 0xE0000000
#define S5P6442_PA_SYSCON 0xE0100000
#define S5P6442_PA_GPIO 0xE0200000
#define S5P6442_PA_VIC0 0xE4000000
#define S5P6442_PA_VIC1 0xE4100000
#define S5P6442_PA_VIC2 0xE4200000
#define S5P6442_PA_SROMC 0xE7000000
#define S5P6442_PA_MDMA 0xE8000000
#define S5P6442_PA_PDMA 0xE9000000
#define S5P6442_PA_TIMER 0xEA000000
#define S5P6442_PA_SYSTIMER 0xEA100000
#define S5P6442_PA_WATCHDOG 0xEA200000
#define S5P6442_PA_UART 0xEC000000
#define S5P6442_PA_IIC0 0xEC100000
#define S5P6442_PA_SPI 0xEC300000
#define S5P6442_PA_PCM0 0xF2400000
#define S5P6442_PA_PCM1 0xF2500000
/* Compatibiltiy Defines */
#define S3C_PA_IIC S5P6442_PA_IIC0
#define S3C_PA_WDT S5P6442_PA_WATCHDOG
#define S5P_PA_CHIPID S5P6442_PA_CHIPID
#define S5P_PA_SDRAM S5P6442_PA_SDRAM
#define S5P_PA_SROMC S5P6442_PA_SROMC
#define S5P_PA_SYSCON S5P6442_PA_SYSCON
#define S5P_PA_TIMER S5P6442_PA_TIMER
/* UART */
#define S3C_PA_UART S5P6442_PA_UART
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */
arch/arm/mach-s5p6442/include/mach/memory.h deleted 100644 → 0
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/* linux/arch/arm/mach-s5p6442/include/mach/memory.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Memory definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PLAT_PHYS_OFFSET UL(0x20000000)
#define CONSISTENT_DMA_SIZE SZ_8M
#endif /* __ASM_ARCH_MEMORY_H */
arch/arm/mach-s5p6442/include/mach/pwm-clock.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
*
* S5P6442 - pwm clock and timer support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PWMCLK_H
#define __ASM_ARCH_PWMCLK_H __FILE__
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg == S3C64XX_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
#endif /* __ASM_ARCH_PWMCLK_H */
arch/arm/mach-s5p6442/include/mach/regs-clock.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P_APLL_LOCK S5P_CLKREG(0x00)
#define S5P_MPLL_LOCK S5P_CLKREG(0x08)
#define S5P_EPLL_LOCK S5P_CLKREG(0x10)
#define S5P_VPLL_LOCK S5P_CLKREG(0x20)
#define S5P_APLL_CON S5P_CLKREG(0x100)
#define S5P_MPLL_CON S5P_CLKREG(0x108)
#define S5P_EPLL_CON S5P_CLKREG(0x110)
#define S5P_VPLL_CON S5P_CLKREG(0x120)
#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
#define S5P_CLK_SRC4 S5P_CLKREG(0x210)
#define S5P_CLK_SRC5 S5P_CLKREG(0x214)
#define S5P_CLK_SRC6 S5P_CLKREG(0x218)
#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280)
#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284)
#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
/* CLK_OUT */
#define S5P_CLK_OUT_SHIFT (12)
#define S5P_CLK_OUT_MASK (0x1F << S5P_CLK_OUT_SHIFT)
#define S5P_CLK_OUT S5P_CLKREG(0x500)
#define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000)
#define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004)
#define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100)
#define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104)
#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
/* Register Bit definition */
#define S5P_EPLL_EN (1<<31)
#define S5P_EPLL_MASK 0xffffffff
#define S5P_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
/* CLKDIV0 */
#define S5P_CLKDIV0_APLL_SHIFT (0)
#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
#define S5P_CLKDIV0_A2M_SHIFT (4)
#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
#define S5P_CLKDIV0_D0CLK_SHIFT (16)
#define S5P_CLKDIV0_D0CLK_MASK (0xF << S5P_CLKDIV0_D0CLK_SHIFT)
#define S5P_CLKDIV0_P0CLK_SHIFT (20)
#define S5P_CLKDIV0_P0CLK_MASK (0x7 << S5P_CLKDIV0_P0CLK_SHIFT)
#define S5P_CLKDIV0_D1CLK_SHIFT (24)
#define S5P_CLKDIV0_D1CLK_MASK (0xF << S5P_CLKDIV0_D1CLK_SHIFT)
#define S5P_CLKDIV0_P1CLK_SHIFT (28)
#define S5P_CLKDIV0_P1CLK_MASK (0x7 << S5P_CLKDIV0_P1CLK_SHIFT)
/* Clock MUX status Registers */
#define S5P_CLK_MUX_STAT0_APLL_SHIFT (0)
#define S5P_CLK_MUX_STAT0_APLL_MASK (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT)
#define S5P_CLK_MUX_STAT0_MPLL_SHIFT (4)
#define S5P_CLK_MUX_STAT0_MPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT)
#define S5P_CLK_MUX_STAT0_EPLL_SHIFT (8)
#define S5P_CLK_MUX_STAT0_EPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT)
#define S5P_CLK_MUX_STAT0_VPLL_SHIFT (12)
#define S5P_CLK_MUX_STAT0_VPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT)
#define S5P_CLK_MUX_STAT0_MUXARM_SHIFT (16)
#define S5P_CLK_MUX_STAT0_MUXARM_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT)
#define S5P_CLK_MUX_STAT0_MUXD0_SHIFT (20)
#define S5P_CLK_MUX_STAT0_MUXD0_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT)
#define S5P_CLK_MUX_STAT0_MUXD1_SHIFT (24)
#define S5P_CLK_MUX_STAT0_MUXD1_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT)
#define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT (24)
#define S5P_CLK_MUX_STAT1_D1SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT)
#define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT (28)
#define S5P_CLK_MUX_STAT1_D0SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT)
#endif /* __ASM_ARCH_REGS_CLOCK_H */
arch/arm/mach-s5p6442/include/mach/regs-irq.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/include/mach/regs-irq.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - IRQ register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_IRQ_H
#define __ASM_ARCH_REGS_IRQ_H __FILE__
#include <asm/hardware/vic.h>
#include <mach/map.h>
#endif /* __ASM_ARCH_REGS_IRQ_H */
arch/arm/mach-s5p6442/include/mach/spi-clocks.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __S5P6442_PLAT_SPI_CLKS_H
#define __S5P6442_PLAT_SPI_CLKS_H __FILE__
#define S5P6442_SPI_SRCCLK_PCLK 0
#define S5P6442_SPI_SRCCLK_SCLK 1
#endif /* __S5P6442_PLAT_SPI_CLKS_H */
arch/arm/mach-s5p6442/include/mach/system.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/include/mach/system.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - system support header
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__
#include <plat/system-reset.h>
static void arch_idle(void)
{
/* nothing here yet */
}
#endif /* __ASM_ARCH_SYSTEM_H */
arch/arm/mach-s5p6442/include/mach/tick.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/include/mach/tick.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Based on arch/arm/mach-s3c6400/include/mach/tick.h
*
* S5P6442 - Timer tick support definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TICK_H
#define __ASM_ARCH_TICK_H __FILE__
static inline u32 s3c24xx_ostimer_pending(void)
{
u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
}
#define TICK_MAX (0xffffffff)
#endif /* __ASM_ARCH_TICK_H */
arch/arm/mach-s5p6442/include/mach/timex.h deleted 100644 → 0
View file @ 014322da
/* arch/arm/mach-s5p6442/include/mach/timex.h
*
* Copyright (c) 2003-2010 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S5P6442 - time parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
* a variable is useless. It seems as long as we make our timers an
* exact multiple of HZ, any value that makes a 1->1 correspondence
* for the time conversion functions to/from jiffies is acceptable.
*/
#define CLOCK_TICK_RATE 12000000
#endif /* __ASM_ARCH_TIMEX_H */
arch/arm/mach-s5p6442/include/mach/uncompress.h deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/include/mach/uncompress.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <mach/map.h>
#include <plat/uncompress.h>
static void arch_detect_cpu(void)
{
/* we do not need to do any cpu detection here at the moment. */
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */
arch/arm/mach-s5p6442/include/mach/vmalloc.h deleted 100644 → 0
View file @ 014322da
/* arch/arm/mach-s5p6442/include/mach/vmalloc.h
*
* Copyright 2010 Ben Dooks <ben-linux@fluff.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S5P6442 vmalloc definition
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
arch/arm/mach-s5p6442/init.c deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/s5p6442-init.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/s5p6442.h>
#include <plat/regs-serial.h>
static struct s3c24xx_uart_clksrc s5p6442_serial_clocks[] = {
[0] = {
.name = "pclk",
.divisor = 1,
.min_baud = 0,
.max_baud = 0,
},
};
/* uart registration process */
void __init s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
struct s3c2410_uartcfg *tcfg = cfg;
u32 ucnt;
for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
if (!tcfg->clocks) {
tcfg->clocks = s5p6442_serial_clocks;
tcfg->clocks_size = ARRAY_SIZE(s5p6442_serial_clocks);
}
}
s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
}
arch/arm/mach-s5p6442/mach-smdk6442.c deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/mach-smdk6442.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/i2c.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <plat/s5p6442.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/iic.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define SMDK6442_ULCON_DEFAULT S3C2410_LCON_CS8
#define SMDK6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)
static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = SMDK6442_UCON_DEFAULT,
.ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = SMDK6442_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = SMDK6442_UCON_DEFAULT,
.ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = SMDK6442_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = SMDK6442_UCON_DEFAULT,
.ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = SMDK6442_UFCON_DEFAULT,
},
};
static struct platform_device *smdk6442_devices[] __initdata = {
&s3c_device_i2c0,
&samsung_asoc_dma,
&s5p6442_device_iis0,
&s3c_device_wdt,
};
static struct i2c_board_info smdk6442_i2c_devs0[] __initdata = {
{ I2C_BOARD_INFO("wm8580", 0x1b), },
};
static void __init smdk6442_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdk6442_uartcfgs, ARRAY_SIZE(smdk6442_uartcfgs));
}
static void __init smdk6442_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
i2c_register_board_info(0, smdk6442_i2c_devs0,
ARRAY_SIZE(smdk6442_i2c_devs0));
platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices));
}
MACHINE_START(SMDK6442, "SMDK6442")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.boot_params = S5P_PA_SDRAM + 0x100,
.init_irq = s5p6442_init_irq,
.map_io = smdk6442_map_io,
.init_machine = smdk6442_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END
arch/arm/mach-s5p6442/setup-i2c0.c deleted 100644 → 0
View file @ 014322da
/* linux/arch/arm/mach-s5p6442/setup-i2c0.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* I2C0 GPIO configuration.
*
* Based on plat-s3c64xx/setup-i2c0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/gpio.h>
struct platform_device; /* don't need the contents */
#include <plat/gpio-cfg.h>
#include <plat/iic.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5P6442_GPD1(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
arch/arm/plat-s5p/Kconfig
View file @ 586893eb
......@@ -7,7 +7,7 @@
config PLAT_S5P
bool
depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
default y
select ARM_VIC if !ARCH_EXYNOS4
select ARM_GIC if ARCH_EXYNOS4
......
arch/arm/plat-s5p/cpu.c
View file @ 586893eb
......@@ -21,7 +21,6 @@
#include <plat/cpu.h>
#include <plat/s5p6440.h>
#include <plat/s5p6442.h>
#include <plat/s5p6450.h>
#include <plat/s5pc100.h>
#include <plat/s5pv210.h>
......@@ -30,7 +29,6 @@
/* table of supported CPUs */
static const char name_s5p6440[] = "S5P6440";
static const char name_s5p6442[] = "S5P6442";
static const char name_s5p6450[] = "S5P6450";
static const char name_s5pc100[] = "S5PC100";
static const char name_s5pv210[] = "S5PV210/S5PC110";
......@@ -45,14 +43,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.init_uarts = s5p6440_init_uarts,
.init = s5p64x0_init,
.name = name_s5p6440,
}, {
.idcode = 0x36442000,
.idmask = 0xfffff000,
.map_io = s5p6442_map_io,
.init_clocks = s5p6442_init_clocks,
.init_uarts = s5p6442_init_uarts,
.init = s5p6442_init,
.name = name_s5p6442,
}, {
.idcode = 0x36450000,
.idmask = 0xfffff000,
......
arch/arm/plat-s5p/include/plat/s5p6442.h deleted 100644 → 0
View file @ 014322da
/* arch/arm/plat-s5p/include/plat/s5p6442.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Header file for s5p6442 cpu support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Common init code for S5P6442 related SoCs */
extern void s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void s5p6442_register_clocks(void);
extern void s5p6442_setup_clocks(void);
#ifdef CONFIG_CPU_S5P6442
extern int s5p6442_init(void);
extern void s5p6442_init_irq(void);
extern void s5p6442_map_io(void);
extern void s5p6442_init_clocks(int xtal);
#define s5p6442_init_uarts s5p6442_common_init_uarts
#else
#define s5p6442_init_clocks NULL
#define s5p6442_init_uarts NULL
#define s5p6442_map_io NULL
#define s5p6442_init NULL
#endif
arch/arm/plat-samsung/include/plat/cpu.h
View file @ 586893eb
......@@ -86,7 +86,6 @@ extern struct sysdev_class s3c2443_sysclass;
extern struct sysdev_class s3c6410_sysclass;
extern struct sysdev_class s3c64xx_sysclass;
extern struct sysdev_class s5p64x0_sysclass;
extern struct sysdev_class s5p6442_sysclass;
extern struct sysdev_class s5pv210_sysclass;
extern struct sysdev_class exynos4_sysclass;
......
arch/arm/plat-samsung/include/plat/debug-macro.S
View file @ 586893eb
......@@ -11,7 +11,7 @@
#include <plat/regs-serial.h>
/* The S5PV210/S5PC110 and S5P6442 implementations are as belows. */
/* The S5PV210/S5PC110 implementations are as belows. */
.macro fifo_level_s5pv210 rd, rx
ldr \rd, [ \rx, # S3C2410_UFSTAT ]
......
arch/arm/plat-samsung/include/plat/devs.h
View file @ 586893eb
......@@ -111,12 +111,6 @@ extern struct platform_device exynos4_device_spdif;
extern struct platform_device exynos4_device_pd[];
extern struct platform_device exynos4_device_ahci;
extern struct platform_device s5p6442_device_pcm0;
extern struct platform_device s5p6442_device_pcm1;
extern struct platform_device s5p6442_device_iis0;
extern struct platform_device s5p6442_device_iis1;
extern struct platform_device s5p6442_device_spi;
extern struct platform_device s5p6440_device_pcm;
extern struct platform_device s5p6440_device_iis;
......
arch/arm/plat-samsung/include/plat/regs-serial.h
View file @ 586893eb
......@@ -194,7 +194,7 @@
#define S3C64XX_UINTSP 0x34
#define S3C64XX_UINTM 0x38
/* Following are specific to S5PV210 and S5P6442 */
/* Following are specific to S5PV210 */
#define S5PV210_UCON_CLKMASK (1<<10)
#define S5PV210_UCON_PCLK (0<<10)
#define S5PV210_UCON_UCLK (1<<10)
......
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
View file @ 586893eb
......@@ -69,6 +69,5 @@ extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
#endif /* __S3C64XX_PLAT_SPI_H */
sound/soc/samsung/Kconfig
View file @ 586893eb
config SND_SOC_SAMSUNG
tristate "ASoC support for Samsung"
depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_EXYNOS4
depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_EXYNOS4
select S3C64XX_DMA if ARCH_S3C64XX
select S3C2410_DMA if ARCH_S3C2410
help
......@@ -55,7 +55,7 @@ config SND_SOC_SAMSUNG_JIVE_WM8750
config SND_SOC_SAMSUNG_SMDK_WM8580
tristate "SoC I2S Audio support for WM8580 on SMDK"
depends on SND_SOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100 || MACH_SMDK6440 || MACH_SMDK6450 || MACH_SMDK6442 || MACH_SMDKV210 || MACH_SMDKC110)
depends on SND_SOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100 || MACH_SMDK6440 || MACH_SMDK6450 || MACH_SMDKV210 || MACH_SMDKC110)
select SND_SOC_WM8580
select SND_SAMSUNG_I2S
help
......
sound/soc/samsung/smdk_wm8580.c
View file @ 586893eb
......@@ -249,7 +249,7 @@ static int __init smdk_audio_init(void)
int ret;
char *str;
if (machine_is_smdkc100() || machine_is_smdk6442()
if (machine_is_smdkc100()
|| machine_is_smdkv210() || machine_is_smdkc110()) {
smdk.num_links = 3;
/* Secondary is at offset SAMSUNG_I2S_SECOFF from Primary */
......
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