Commit 58b3d12c authored by Paolo Bonzini's avatar Paolo Bonzini

KVM: x86: add support for CPUID leaf 0x80000021

CPUID leaf 0x80000021 defines some features (or lack of bugs) of AMD
processors.  Expose the ones that make sense via KVM_GET_SUPPORTED_CPUID.
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent bf07be36
...@@ -1068,7 +1068,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) ...@@ -1068,7 +1068,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
entry->edx = 0; entry->edx = 0;
break; break;
case 0x80000000: case 0x80000000:
entry->eax = min(entry->eax, 0x8000001f); entry->eax = min(entry->eax, 0x80000021);
break; break;
case 0x80000001: case 0x80000001:
cpuid_entry_override(entry, CPUID_8000_0001_EDX); cpuid_entry_override(entry, CPUID_8000_0001_EDX);
...@@ -1139,6 +1139,23 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) ...@@ -1139,6 +1139,23 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
entry->ebx &= ~GENMASK(11, 6); entry->ebx &= ~GENMASK(11, 6);
} }
break; break;
case 0x80000020:
entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
break;
case 0x80000021:
entry->ebx = entry->ecx = entry->edx = 0;
/*
* Pass down these bits:
* EAX 0 NNDBP, Processor ignores nested data breakpoints
* EAX 2 LAS, LFENCE always serializing
* EAX 6 NSCB, Null selector clear base
*
* Other defined bits are for MSRs that KVM does not expose:
* EAX 3 SPCL, SMM page configuration lock
* EAX 13 PCMSR, Prefetch control MSR
*/
entry->eax &= BIT(0) | BIT(2) | BIT(6);
break;
/*Add support for Centaur's CPUID instruction*/ /*Add support for Centaur's CPUID instruction*/
case 0xC0000000: case 0xC0000000:
/*Just support up to 0xC0000004 now*/ /*Just support up to 0xC0000004 now*/
......
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