Commit 5a31be3f authored by Greg Ungerer's avatar Greg Ungerer Committed by Linus Torvalds

[PATCH] m68knommu: memory register defines for 520x ColdFire CPU's

Here is a small patch to automatically detect the DRAM size on m520x.
It was generated against 2.6.17-uc0, and tested on an Intec 5208 dev board.

(This part of the patch if the memory register defines for the 520x
ColdFire CPU family - Greg).
Signed-off-by: default avatarMichael Broughton <mbobowik@telusplanet.net>
Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 55298405
...@@ -31,6 +31,16 @@ ...@@ -31,6 +31,16 @@
#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ #define MCFINT_QSPI 31 /* Interrupt number for QSPI */
#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
/*
* SDRAM configuration registers.
*/
#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */
#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */
#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */
#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */
#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
#define MCF_GPIO_PAR_UART (0xA4036) #define MCF_GPIO_PAR_UART (0xA4036)
#define MCF_GPIO_PAR_FECI2C (0xA4033) #define MCF_GPIO_PAR_FECI2C (0xA4033)
...@@ -47,7 +57,7 @@ ...@@ -47,7 +57,7 @@
#define ICR_INTRCONF 0x05 #define ICR_INTRCONF 0x05
#define MCFPIT_IMR MCFINTC_IMRL #define MCFPIT_IMR MCFINTC_IMRL
#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) #define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
/****************************************************************************/ /****************************************************************************/
#endif /* m520xsim_h */ #endif /* m520xsim_h */
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