dt-bindings: display/msm: move common MDSS properties to mdss-common.yaml

Move properties common to all MDSS DT nodes to the mdss-common.yaml. This extends qcom,msm8998-mdss schema to allow interconnect nodes, which will be added later, once msm8998 gains interconnect support. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/508385/ Link: https://lore.kernel.org/r/20221024164225.3236654-6-dmitry.baryshkov@linaro.orgSigned-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

dt-bindings: display/msm: move common MDSS properties to mdss-common.yaml
Move properties common to all MDSS DT nodes to the mdss-common.yaml. This extends qcom,msm8998-mdss schema to allow interconnect nodes, which will be added later, once msm8998 gains interconnect support. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/508385/ Link: https://lore.kernel.org/r/20221024164225.3236654-6-dmitry.baryshkov@linaro.orgSigned-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
5a5c7b35 · Dmitry Baryshkov · c3d7f3e7 · 5a5c7b35 · 5a5c7b35 · 5a5c7b35
Commit 5a5c7b35 authored Oct 24, 2022 by Dmitry Baryshkov
6 changed files
--- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
@@ -14,20 +14,13 @@ description: |
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS and DPU are mentioned for MSM8998 target.
+$ref: /schemas/display/msm/mdss-common.yaml#
 properties:
  compatible:
    items:
      - const: qcom,msm8998-mdss
-  reg:
-    maxItems: 1
-  reg-names:
-    const: mdss
-  power-domains:
-    maxItems: 1
  clocks:
    items:
      - description: Display AHB clock
@@ -40,23 +33,8 @@ properties:
      - const: bus
      - const: core
-  interrupts:
-    maxItems: 1
-  interrupt-controller: true
-  "#address-cells": true
-  "#size-cells": true
-  "#interrupt-cells":
-    const: 1
  iommus:
-    items:
+    maxItems: 1
-      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
-  ranges: true
 patternProperties:
  "^display-controller@[0-9a-f]+$":
@@ -100,18 +78,7 @@ patternProperties:
          - const: core
          - const: vsync
-required:
+unevaluatedProperties: false
-  - compatible
-  - reg
-  - reg-names
-  - power-domains
-  - clocks
-  - interrupts
-  - interrupt-controller
-  - iommus
-  - ranges
-additionalProperties: false
 examples:
  - |

--- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
@@ -14,20 +14,13 @@ description: |
  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
  and DPU are mentioned for QCM2290 target.
+$ref: /schemas/display/msm/mdss-common.yaml#
 properties:
  compatible:
    items:
      - const: qcom,qcm2290-mdss
-  reg:
-    maxItems: 1
-  reg-names:
-    const: mdss
-  power-domains:
-    maxItems: 1
  clocks:
    items:
      - description: Display AHB clock from gcc
@@ -40,35 +33,14 @@ properties:
      - const: bus
      - const: core
-  interrupts:
-    maxItems: 1
-  interrupt-controller: true
-  "#address-cells": true
-  "#size-cells": true
-  "#interrupt-cells":
-    const: 1
  iommus:
-    items:
+    maxItems: 2
-      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
-      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
-  ranges: true
  interconnects:
-    items:
+    maxItems: 1
-      - description: Interconnect path specifying the port ids for data bus
  interconnect-names:
-    const: mdp0-mem
+    maxItems: 1
-  resets:
-    items:
-      - description: MDSS_CORE reset
 patternProperties:
  "^display-controller@[0-9a-f]+$":
@@ -108,18 +80,7 @@ patternProperties:
          - const: lut
          - const: vsync
-required:
+unevaluatedProperties: false
-  - compatible
-  - reg
-  - reg-names
-  - power-domains
-  - clocks
-  - interrupts
-  - interrupt-controller
-  - iommus
-  - ranges
-additionalProperties: false
 examples:
  - |

--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
@@ -14,20 +14,13 @@ description: |
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS and DPU are mentioned for SC7180 target.
+$ref: /schemas/display/msm/mdss-common.yaml#
 properties:
  compatible:
    items:
      - const: qcom,sc7180-mdss
-  reg:
-    maxItems: 1
-  reg-names:
-    const: mdss
-  power-domains:
-    maxItems: 1
  clocks:
    items:
      - description: Display AHB clock from gcc
@@ -40,34 +33,14 @@ properties:
      - const: ahb
      - const: core
-  interrupts:
-    maxItems: 1
-  interrupt-controller: true
-  "#address-cells": true
-  "#size-cells": true
-  "#interrupt-cells":
-    const: 1
  iommus:
-    items:
+    maxItems: 1
-      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
-  ranges: true
  interconnects:
-    items:
+    maxItems: 1
-      - description: Interconnect path specifying the port ids for data bus
  interconnect-names:
-    const: mdp0-mem
+    maxItems: 1
-  resets:
-    items:
-      - description: MDSS_CORE reset
 patternProperties:
  "^display-controller@[0-9a-f]+$":
@@ -109,18 +82,7 @@ patternProperties:
          - const: core
          - const: vsync
-required:
+unevaluatedProperties: false
-  - compatible
-  - reg
-  - reg-names
-  - power-domains
-  - clocks
-  - interrupts
-  - interrupt-controller
-  - iommus
-  - ranges
-additionalProperties: false
 examples:
  - |

--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
@@ -14,19 +14,12 @@ description: |
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS and DPU are mentioned for SC7280.
+$ref: /schemas/display/msm/mdss-common.yaml#
 properties:
  compatible:
    const: qcom,sc7280-mdss
-  reg:
-    maxItems: 1
-  reg-names:
-    const: mdss
-  power-domains:
-    maxItems: 1
  clocks:
    items:
      - description: Display AHB clock from gcc
@@ -39,34 +32,14 @@ properties:
      - const: ahb
      - const: core
-  interrupts:
-    maxItems: 1
-  interrupt-controller: true
-  "#address-cells": true
-  "#size-cells": true
-  "#interrupt-cells":
-    const: 1
  iommus:
-    items:
+    maxItems: 1
-      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
-  ranges: true
  interconnects:
-    items:
+    maxItems: 1
-      - description: Interconnect path specifying the port ids for data bus
  interconnect-names:
-    const: mdp0-mem
+    maxItems: 1
-  resets:
-    items:
-      - description: MDSS_CORE reset
 patternProperties:
  "^display-controller@[0-9a-f]+$":
@@ -107,18 +80,7 @@ patternProperties:
          - const: core
          - const: vsync
-required:
+unevaluatedProperties: false
-  - compatible
-  - reg
-  - reg-names
-  - power-domains
-  - clocks
-  - interrupts
-  - interrupt-controller
-  - iommus
-  - ranges
-additionalProperties: false
 examples:
  - |

--- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
@@ -14,20 +14,13 @@ description: |
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS and DPU are mentioned for SDM845 target.
+$ref: /schemas/display/msm/mdss-common.yaml#
 properties:
  compatible:
    items:
      - const: qcom,sdm845-mdss
-  reg:
-    maxItems: 1
-  reg-names:
-    const: mdss
-  power-domains:
-    maxItems: 1
  clocks:
    items:
      - description: Display AHB clock from gcc
@@ -38,38 +31,14 @@ properties:
      - const: iface
      - const: core
-  interrupts:
-    maxItems: 1
-  interrupt-controller: true
-  "#address-cells": true
-  "#size-cells": true
-  "#interrupt-cells":
-    const: 1
  iommus:
-    items:
+    maxItems: 2
-      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
-      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
-  ranges: true
  interconnects:
-    items:
+    maxItems: 2
-      - description: Interconnect path from mdp0 port to the data bus
-      - description: Interconnect path from mdp1 port to the data bus
  interconnect-names:
-    items:
+    maxItems: 2
-      - const: mdp0-mem
-      - const: mdp1-mem
-  resets:
-    items:
-      - description: MDSS_CORE reset
 patternProperties:
  "^display-controller@[0-9a-f]+$":
@@ -109,18 +78,7 @@ patternProperties:
          - const: core
          - const: vsync
-required:
+unevaluatedProperties: false
-  - compatible
-  - reg
-  - reg-names
-  - power-domains
-  - clocks
-  - interrupts
-  - interrupt-controller
-  - iommus
-  - ranges
-additionalProperties: false
 examples:
  - |

--- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/mdss-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Qualcomm Display MDSS common properties
+maintainers:
+  - Krishna Manikandan <quic_mkrishn@quicinc.com>
+  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+  - Rob Clark <robdclark@gmail.com>
+description:
+  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+  sub-blocks like DPU display controller, DSI and DP interfaces etc.
+properties:
+  reg:
+    maxItems: 1
+  reg-names:
+    const: mdss
+  power-domains:
+    maxItems: 1
+  clocks:
+    minItems: 2
+    maxItems: 3
+  clock-names:
+    minItems: 2
+    maxItems: 3
+  interrupts:
+    maxItems: 1
+  interrupt-controller: true
+  "#address-cells": true
+  "#size-cells": true
+  "#interrupt-cells":
+    const: 1
+  iommus:
+    minItems: 1
+    items:
+      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
+      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
+  ranges: true
+  interconnects:
+    minItems: 1
+    items:
+      - description: Interconnect path from mdp0 (or a single mdp) port to the data bus
+      - description: Interconnect path from mdp1 port to the data bus
+  interconnect-names:
+    minItems: 1
+    items:
+      - const: mdp0-mem
+      - const: mdp1-mem
+  resets:
+    items:
+      - description: MDSS_CORE reset
+required:
+  - compatible
+  - reg
+  - reg-names
+  - power-domains
+  - clocks
+  - interrupts
+  - interrupt-controller
+  - iommus
+  - ranges
+additionalProperties: true