Commit 5a7c7d14 authored by Sean Christopherson's avatar Sean Christopherson

KVM: selftests: Play nice with AMD's AVIC errata

When AVIC, and thus IPI virtualization on AMD, is enabled, the CPU will
virtualize ICR writes.  Unfortunately, the CPU doesn't do a very good job,
as it fails to clear the BUSY bit and also allows writing ICR2[23:0],
despite them being "RESERVED MBZ".  Account for the quirky behavior in
the xapic_state test to avoid failures in a configuration that likely has
no hope of ever being enabled in production.

Link: https://lore.kernel.org/r/20240719235107.3023592-11-seanjc@google.comSigned-off-by: default avatarSean Christopherson <seanjc@google.com>
parent 0cb26ec3
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
struct xapic_vcpu { struct xapic_vcpu {
struct kvm_vcpu *vcpu; struct kvm_vcpu *vcpu;
bool is_x2apic; bool is_x2apic;
bool has_xavic_errata;
}; };
static void xapic_guest_code(void) static void xapic_guest_code(void)
...@@ -79,12 +80,17 @@ static void ____test_icr(struct xapic_vcpu *x, uint64_t val) ...@@ -79,12 +80,17 @@ static void ____test_icr(struct xapic_vcpu *x, uint64_t val)
vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic); vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic);
icr = (u64)(*((u32 *)&xapic.regs[APIC_ICR])) | icr = (u64)(*((u32 *)&xapic.regs[APIC_ICR])) |
(u64)(*((u32 *)&xapic.regs[APIC_ICR2])) << 32; (u64)(*((u32 *)&xapic.regs[APIC_ICR2])) << 32;
if (!x->is_x2apic) if (!x->is_x2apic) {
val &= (-1u | (0xffull << (32 + 24))); if (!x->has_xavic_errata)
else if (val & X2APIC_RSVD_BITS_MASK) val &= (-1u | (0xffull << (32 + 24)));
} else if (val & X2APIC_RSVD_BITS_MASK) {
return; return;
}
TEST_ASSERT_EQ(icr, val & ~APIC_ICR_BUSY); if (x->has_xavic_errata)
TEST_ASSERT_EQ(icr & ~APIC_ICR_BUSY, val & ~APIC_ICR_BUSY);
else
TEST_ASSERT_EQ(icr, val & ~APIC_ICR_BUSY);
} }
static void __test_icr(struct xapic_vcpu *x, uint64_t val) static void __test_icr(struct xapic_vcpu *x, uint64_t val)
...@@ -236,6 +242,15 @@ int main(int argc, char *argv[]) ...@@ -236,6 +242,15 @@ int main(int argc, char *argv[])
vm = vm_create_with_one_vcpu(&x.vcpu, xapic_guest_code); vm = vm_create_with_one_vcpu(&x.vcpu, xapic_guest_code);
x.is_x2apic = false; x.is_x2apic = false;
/*
* AMD's AVIC implementation is buggy (fails to clear the ICR BUSY bit),
* and also diverges from KVM with respect to ICR2[23:0] (KVM and Intel
* drops writes, AMD does not). Account for the errata when checking
* that KVM reads back what was written.
*/
x.has_xavic_errata = host_cpu_is_amd &&
get_kvm_amd_param_bool("avic");
vcpu_clear_cpuid_feature(x.vcpu, X86_FEATURE_X2APIC); vcpu_clear_cpuid_feature(x.vcpu, X86_FEATURE_X2APIC);
virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA); virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
......
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