Commit 5bc35703 authored by Dan Carpenter's avatar Dan Carpenter Committed by Herbert Xu

crypto: tegra-aes - bitwise vs logical and

The bug here is that:

	while (eng_busy & (!icq_empty) & dma_busy)

is never true because it's using bitwise instead of logical ANDs.  The
other bitwise AND conditions work as intended but I changed them as well
for consistency.
Signed-off-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 393e661d
...@@ -275,7 +275,7 @@ static int aes_start_crypt(struct tegra_aes_dev *dd, u32 in_addr, u32 out_addr, ...@@ -275,7 +275,7 @@ static int aes_start_crypt(struct tegra_aes_dev *dd, u32 in_addr, u32 out_addr,
value = aes_readl(dd, TEGRA_AES_INTR_STATUS); value = aes_readl(dd, TEGRA_AES_INTR_STATUS);
eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD; eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD;
icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD; icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD;
} while (eng_busy & (!icq_empty)); } while (eng_busy && !icq_empty);
aes_writel(dd, cmdq[i], TEGRA_AES_ICMDQUE_WR); aes_writel(dd, cmdq[i], TEGRA_AES_ICMDQUE_WR);
} }
...@@ -365,7 +365,7 @@ static int aes_set_key(struct tegra_aes_dev *dd) ...@@ -365,7 +365,7 @@ static int aes_set_key(struct tegra_aes_dev *dd)
eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD; eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD;
icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD; icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD;
dma_busy = value & TEGRA_AES_DMA_BUSY_FIELD; dma_busy = value & TEGRA_AES_DMA_BUSY_FIELD;
} while (eng_busy & (!icq_empty) & dma_busy); } while (eng_busy && !icq_empty && dma_busy);
/* settable command to get key into internal registers */ /* settable command to get key into internal registers */
value = CMD_SETTABLE << CMDQ_OPCODE_SHIFT | value = CMD_SETTABLE << CMDQ_OPCODE_SHIFT |
...@@ -379,7 +379,7 @@ static int aes_set_key(struct tegra_aes_dev *dd) ...@@ -379,7 +379,7 @@ static int aes_set_key(struct tegra_aes_dev *dd)
value = aes_readl(dd, TEGRA_AES_INTR_STATUS); value = aes_readl(dd, TEGRA_AES_INTR_STATUS);
eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD; eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD;
icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD; icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD;
} while (eng_busy & (!icq_empty)); } while (eng_busy && !icq_empty);
return 0; return 0;
} }
......
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