Commit 5c8a86e1 authored by Felipe Balbi's avatar Felipe Balbi

usb: musb: drop unneeded musb_debug trickery

We have a generic way of enabling/disabling
different debug messages on a driver called
DYNAMIC_PRINTK. Anyone interested in enabling
just part of the debug messages, please read
the documentation under:

Documentation/dynamic-debug-howto.txt

for information on how to use that great
infrastructure.
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent a0885924
......@@ -176,11 +176,3 @@ config USB_TUSB_OMAP_DMA
help
Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
config USB_MUSB_DEBUG
depends on USB_MUSB_HDRC
bool "Enable debugging messages"
default n
help
This enables musb debugging. To set the logging level use the debug
module parameter. Starting at level 3, per-transfer (urb, usb_request,
packet, or dma transfer) tracing may kick in.
......@@ -2,8 +2,6 @@
# for USB OTG silicon based on Mentor Graphics INVENTRA designs
#
ccflags-$(CONFIG_USB_MUSB_DEBUG) := -DDEBUG
obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o
musb_hdrc-y := musb_core.o
......
......@@ -151,7 +151,7 @@ static void otg_timer(unsigned long _musb)
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
DBG(7, "Poll devctl %02x (%s)\n", devctl,
dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
......@@ -203,7 +203,7 @@ static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || (musb->a_wait_bcon == 0 &&
musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
DBG(4, "%s active, deleting timer\n",
dev_dbg(musb->controller, "%s active, deleting timer\n",
otg_state_string(musb->xceiv->state));
del_timer(&otg_workaround);
last_timer = jiffies;
......@@ -211,12 +211,12 @@ static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
}
if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
DBG(4, "Longer idle timer already pending, ignoring...\n");
dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
return;
}
last_timer = timeout;
DBG(4, "%s inactive, starting idle timer for %u ms\n",
dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
otg_state_string(musb->xceiv->state),
jiffies_to_msecs(timeout - jiffies));
mod_timer(&otg_workaround, timeout);
......@@ -305,7 +305,7 @@ static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
}
/* NOTE: this must complete power-on within 100 ms. */
DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
......
......@@ -43,7 +43,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
musb_writew(epio, MUSB_TXCOUNT, len);
DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
hw_ep->epnum, fifo, len, src, epio);
dump_fifo_data(src, len);
......@@ -154,7 +154,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
}
}
DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'R', hw_ep->epnum, fifo, len, dst);
dump_fifo_data(dst, len);
......@@ -279,13 +279,14 @@ static void musb_conn_timer_handler(unsigned long _musb)
}
break;
default:
DBG(1, "%s state not handled\n",
dev_dbg(musb->controller, "%s state not handled\n",
otg_state_string(musb->xceiv->state));
break;
}
spin_unlock_irqrestore(&musb->lock, flags);
DBG(4, "state is %s\n", otg_state_string(musb->xceiv->state));
dev_dbg(musb->controller, "state is %s\n",
otg_state_string(musb->xceiv->state));
}
static void bfin_musb_enable(struct musb *musb)
......@@ -307,7 +308,7 @@ static void bfin_musb_set_vbus(struct musb *musb, int is_on)
value = !value;
gpio_set_value(musb->config->gpio_vrsel, value);
DBG(1, "VBUS %s, devctl %02x "
dev_dbg(musb->controller, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL));
......
......@@ -236,7 +236,7 @@ static int cppi_controller_stop(struct dma_controller *c)
musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
DAVINCI_DMA_ALL_CHANNELS_ENABLE);
DBG(1, "Tearing down RX and TX Channels\n");
dev_dbg(musb->controller, "Tearing down RX and TX Channels\n");
for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
/* FIXME restructure of txdma to use bds like rxdma */
controller->tx[i].last_processed = NULL;
......@@ -301,13 +301,13 @@ cppi_channel_allocate(struct dma_controller *c,
*/
if (transmit) {
if (index >= ARRAY_SIZE(controller->tx)) {
DBG(1, "no %cX%d CPPI channel\n", 'T', index);
dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'T', index);
return NULL;
}
cppi_ch = controller->tx + index;
} else {
if (index >= ARRAY_SIZE(controller->rx)) {
DBG(1, "no %cX%d CPPI channel\n", 'R', index);
dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'R', index);
return NULL;
}
cppi_ch = controller->rx + index;
......@@ -318,13 +318,13 @@ cppi_channel_allocate(struct dma_controller *c,
* with the other DMA engine too
*/
if (cppi_ch->hw_ep)
DBG(1, "re-allocating DMA%d %cX channel %p\n",
dev_dbg(musb->controller, "re-allocating DMA%d %cX channel %p\n",
index, transmit ? 'T' : 'R', cppi_ch);
cppi_ch->hw_ep = ep;
cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
cppi_ch->channel.max_len = 0x7fffffff;
DBG(4, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');
dev_dbg(musb->controller, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');
return &cppi_ch->channel;
}
......@@ -339,7 +339,7 @@ static void cppi_channel_release(struct dma_channel *channel)
c = container_of(channel, struct cppi_channel, channel);
tibase = c->controller->tibase;
if (!c->hw_ep)
DBG(1, "releasing idle DMA channel %p\n", c);
dev_dbg(musb->controller, "releasing idle DMA channel %p\n", c);
else if (!c->transmit)
core_rxirq_enable(tibase, c->index + 1);
......@@ -597,7 +597,7 @@ cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
length = min(n_bds * maxpacket, length);
}
DBG(4, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",
dev_dbg(musb->controller, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",
tx->index,
maxpacket,
rndis ? "rndis" : "transparent",
......@@ -654,7 +654,7 @@ cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
bd->hw_options |= CPPI_ZERO_SET;
}
DBG(5, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",
dev_dbg(musb->controller, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",
bd, bd->hw_next, bd->hw_bufp,
bd->hw_off_len, bd->hw_options);
......@@ -819,7 +819,7 @@ cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
length = min(n_bds * maxpacket, length);
DBG(4, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
dev_dbg(musb->controller, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
"dma 0x%llx len %u %u/%u\n",
rx->index, maxpacket,
onepacket
......@@ -936,7 +936,7 @@ cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
& 0xffff;
if (i < (2 + n_bds)) {
DBG(2, "bufcnt%d underrun - %d (for %d)\n",
dev_dbg(musb->controller, "bufcnt%d underrun - %d (for %d)\n",
rx->index, i, n_bds);
musb_writel(tibase,
DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
......@@ -985,7 +985,7 @@ static int cppi_channel_program(struct dma_channel *ch,
/* WARN_ON(1); */
break;
case MUSB_DMA_STATUS_UNKNOWN:
DBG(1, "%cX DMA%d not allocated!\n",
dev_dbg(musb->controller, "%cX DMA%d not allocated!\n",
cppi_ch->transmit ? 'T' : 'R',
cppi_ch->index);
/* FALLTHROUGH */
......@@ -1040,7 +1040,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
if (!completed && (bd->hw_options & CPPI_OWN_SET))
break;
DBG(5, "C/RXBD %llx: nxt %08x buf %08x "
dev_dbg(musb->controller, "C/RXBD %llx: nxt %08x buf %08x "
"off.len %08x opt.len %08x (%d)\n",
(unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp,
bd->hw_off_len, bd->hw_options,
......@@ -1062,7 +1062,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
* CPPI ignores those BDs even though OWN is still set.
*/
completed = true;
DBG(3, "rx short %d/%d (%d)\n",
dev_dbg(musb->controller, "rx short %d/%d (%d)\n",
len, bd->buflen,
rx->channel.actual_len);
}
......@@ -1112,7 +1112,7 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
musb_ep_select(cppi->mregs, rx->index + 1);
csr = musb_readw(regs, MUSB_RXCSR);
if (csr & MUSB_RXCSR_DMAENAB) {
DBG(4, "list%d %p/%p, last %llx%s, csr %04x\n",
dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
rx->index,
rx->head, rx->tail,
rx->last_processed
......@@ -1175,7 +1175,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
return IRQ_NONE;
}
DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
dev_dbg(musb->controller, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
/* process TX channels */
for (index = 0; tx; tx = tx >> 1, index++) {
......@@ -1203,7 +1203,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
* that needs to be acknowledged.
*/
if (NULL == bd) {
DBG(1, "null BD\n");
dev_dbg(musb->controller, "null BD\n");
musb_writel(&tx_ram->tx_complete, 0, 0);
continue;
}
......@@ -1218,7 +1218,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id)
if (bd->hw_options & CPPI_OWN_SET)
break;
DBG(5, "C/TXBD %p n %x b %x off %x opt %x\n",
dev_dbg(musb->controller, "C/TXBD %p n %x b %x off %x opt %x\n",
bd, bd->hw_next, bd->hw_bufp,
bd->hw_off_len, bd->hw_options);
......
......@@ -199,7 +199,7 @@ static void otg_timer(unsigned long _musb)
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
DBG(7, "Poll devctl %02x (%s)\n", devctl,
dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
......@@ -274,7 +274,7 @@ static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || (musb->a_wait_bcon == 0 &&
musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
DBG(4, "%s active, deleting timer\n",
dev_dbg(musb->controller, "%s active, deleting timer\n",
otg_state_string(musb->xceiv->state));
del_timer(&otg_workaround);
last_timer = jiffies;
......@@ -282,12 +282,12 @@ static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
}
if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
DBG(4, "Longer idle timer already pending, ignoring...\n");
dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
return;
}
last_timer = timeout;
DBG(4, "%s inactive, starting idle timer for %u ms\n",
dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
otg_state_string(musb->xceiv->state),
jiffies_to_msecs(timeout - jiffies));
mod_timer(&otg_workaround, timeout);
......@@ -314,7 +314,7 @@ static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
goto eoi;
musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
DBG(4, "USB IRQ %08x\n", status);
dev_dbg(musb->controller, "USB IRQ %08x\n", status);
musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
......@@ -366,7 +366,7 @@ static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
}
DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
......@@ -413,7 +413,7 @@ static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
break;
#endif
default:
DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
}
__raw_writel(cfgchip2, CFGCHIP2);
......
......@@ -220,7 +220,7 @@ static void otg_timer(unsigned long _musb)
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
DBG(7, "poll devctl %02x (%s)\n", devctl,
dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
......@@ -298,7 +298,7 @@ static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
/* ack and handle non-CPPI interrupts */
tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
DBG(4, "IRQ %08x\n", tmp);
dev_dbg(musb->controller, "IRQ %08x\n", tmp);
musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
>> DAVINCI_USB_RXINT_SHIFT;
......@@ -355,7 +355,7 @@ static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
* (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
*/
davinci_musb_source_power(musb, drvvbus, 0);
DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
......@@ -485,7 +485,7 @@ static int davinci_musb_exit(struct musb *musb)
break;
if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
warn = devctl & MUSB_DEVCTL_VBUS;
DBG(1, "VBUS %d\n",
dev_dbg(musb->controller, "VBUS %d\n",
warn >> MUSB_DEVCTL_VBUS_SHIFT);
}
msleep(1000);
......@@ -494,7 +494,7 @@ static int davinci_musb_exit(struct musb *musb)
/* in OTG mode, another host might be connected */
if (devctl & MUSB_DEVCTL_VBUS)
DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
}
phy_off();
......
This diff is collapsed.
......@@ -42,18 +42,6 @@
#define INFO(fmt, args...) yprintk(KERN_INFO, fmt, ## args)
#define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
#define DBG(level, format, args...) do { \
if (_dbg_level(level)) \
pr_debug("%s %d: " format, __func__, __LINE__, ## args); \
} while (0)
extern unsigned musb_debug;
static inline int _dbg_level(unsigned l)
{
return musb_debug >= l;
}
#ifdef CONFIG_DEBUG_FS
extern int musb_init_debugfs(struct musb *musb);
extern void musb_exit_debugfs(struct musb *musb);
......
This diff is collapsed.
......@@ -209,7 +209,7 @@ static inline void musb_try_b_hnp_enable(struct musb *musb)
void __iomem *mbase = musb->mregs;
u8 devctl;
DBG(1, "HNP: Setting HR\n");
dev_dbg(musb->controller, "HNP: Setting HR\n");
devctl = musb_readb(mbase, MUSB_DEVCTL);
musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
}
......@@ -306,7 +306,7 @@ __acquires(musb->lock)
/* Maybe start the first request in the queue */
request = next_request(musb_ep);
if (!musb_ep->busy && request) {
DBG(3, "restarting the request\n");
dev_dbg(musb->controller, "restarting the request\n");
musb_ep_restart(musb, request);
}
......@@ -553,7 +553,7 @@ static void ep0_txstate(struct musb *musb)
if (!req) {
/* WARN_ON(1); */
DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
return;
}
......@@ -610,7 +610,7 @@ musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
/* NOTE: earlier 2.6 versions changed setup packets to host
* order, but now USB packets always stay in USB byte order.
*/
DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
dev_dbg(musb->controller, "SETUP req%02x.%02x v%04x i%04x l%d\n",
req->bRequestType,
req->bRequest,
le16_to_cpu(req->wValue),
......@@ -678,7 +678,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
csr = musb_readw(regs, MUSB_CSR0);
len = musb_readb(regs, MUSB_COUNT0);
DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
csr, len,
musb_readb(mbase, MUSB_FADDR),
decode_ep0stage(musb->ep0_state));
......@@ -749,7 +749,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
/* enter test mode if needed (exit by reset) */
else if (musb->test_mode) {
DBG(1, "entering TESTMODE\n");
dev_dbg(musb->controller, "entering TESTMODE\n");
if (MUSB_TEST_PACKET == musb->test_mode_nr)
musb_load_testpacket(musb);
......@@ -861,7 +861,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
break;
}
DBG(3, "handled %d, csr %04x, ep0stage %s\n",
dev_dbg(musb->controller, "handled %d, csr %04x, ep0stage %s\n",
handled, csr,
decode_ep0stage(musb->ep0_state));
......@@ -878,7 +878,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
if (handled < 0) {
musb_ep_select(mbase, 0);
stall:
DBG(3, "stall (%d)\n", handled);
dev_dbg(musb->controller, "stall (%d)\n", handled);
musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
musb->ep0_state = MUSB_EP0_STAGE_IDLE;
finish:
......@@ -958,7 +958,7 @@ musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
status = 0;
break;
default:
DBG(1, "ep0 request queued in state %d\n",
dev_dbg(musb->controller, "ep0 request queued in state %d\n",
musb->ep0_state);
status = -EINVAL;
goto cleanup;
......@@ -967,7 +967,7 @@ musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
/* add request to the list */
list_add_tail(&req->list, &ep->req_list);
DBG(3, "queue to %s (%s), length=%d\n",
dev_dbg(musb->controller, "queue to %s (%s), length=%d\n",
ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
req->request.length);
......@@ -1060,7 +1060,7 @@ static int musb_g_ep0_halt(struct usb_ep *e, int value)
musb->ackpend = 0;
break;
default:
DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);
status = -EINVAL;
}
......
This diff is collapsed.
......@@ -74,7 +74,7 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
break;
}
DBG(3, "Root port suspended, power %02x\n", power);
dev_dbg(musb->controller, "Root port suspended, power %02x\n", power);
musb->port1_status |= USB_PORT_STAT_SUSPEND;
switch (musb->xceiv->state) {
......@@ -97,7 +97,7 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
break;
#endif
default:
DBG(1, "bogus rh suspend? %s\n",
dev_dbg(musb->controller, "bogus rh suspend? %s\n",
otg_state_string(musb->xceiv->state));
}
} else if (power & MUSB_POWER_SUSPENDM) {
......@@ -105,7 +105,7 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
power |= MUSB_POWER_RESUME;
musb_writeb(mbase, MUSB_POWER, power);
DBG(3, "Root port resuming, power %02x\n", power);
dev_dbg(musb->controller, "Root port resuming, power %02x\n", power);
/* later, GetPortStatus will stop RESUME signaling */
musb->port1_status |= MUSB_PORT_STAT_RESUME;
......@@ -120,7 +120,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
#ifdef CONFIG_USB_MUSB_OTG
if (musb->xceiv->state == OTG_STATE_B_IDLE) {
DBG(2, "HNP: Returning from HNP; no hub reset from b_idle\n");
dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
musb->port1_status &= ~USB_PORT_STAT_RESET;
return;
}
......@@ -159,7 +159,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
musb->port1_status &= ~USB_PORT_STAT_ENABLE;
musb->rh_timer = jiffies + msecs_to_jiffies(50);
} else {
DBG(4, "root port reset stopped\n");
dev_dbg(musb->controller, "root port reset stopped\n");
musb_writeb(mbase, MUSB_POWER,
power & ~MUSB_POWER_RESET);
......@@ -167,7 +167,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
power = musb_readb(mbase, MUSB_POWER);
if (power & MUSB_POWER_HSMODE) {
DBG(4, "high-speed device connected\n");
dev_dbg(musb->controller, "high-speed device connected\n");
musb->port1_status |= USB_PORT_STAT_HIGH_SPEED;
}
......@@ -208,7 +208,7 @@ void musb_root_disconnect(struct musb *musb)
musb->xceiv->state = OTG_STATE_B_IDLE;
break;
default:
DBG(1, "host disconnect (%s)\n",
dev_dbg(musb->controller, "host disconnect (%s)\n",
otg_state_string(musb->xceiv->state));
}
}
......@@ -288,7 +288,7 @@ int musb_hub_control(
default:
goto error;
}
DBG(5, "clear feature %d\n", wValue);
dev_dbg(musb->controller, "clear feature %d\n", wValue);
musb->port1_status &= ~(1 << wValue);
break;
case GetHubDescriptor:
......@@ -330,7 +330,7 @@ int musb_hub_control(
power = musb_readb(musb->mregs, MUSB_POWER);
power &= ~MUSB_POWER_RESUME;
DBG(4, "root port resume stopped, power %02x\n",
dev_dbg(musb->controller, "root port resume stopped, power %02x\n",
power);
musb_writeb(musb->mregs, MUSB_POWER, power);
......@@ -353,7 +353,7 @@ int musb_hub_control(
(__le32 *) buf);
/* port change status is more interesting */
DBG(get_unaligned((u16 *)(buf+2)) ? 2 : 5, "port status %08x\n",
dev_dbg(musb->controller, "port status %08x\n",
musb->port1_status);
break;
case SetPortFeature:
......@@ -424,7 +424,7 @@ int musb_hub_control(
default:
goto error;
}
DBG(5, "set feature %d\n", wValue);
dev_dbg(musb->controller, "set feature %d\n", wValue);
musb->port1_status |= 1 << wValue;
break;
......
......@@ -122,11 +122,12 @@ static void configure_channel(struct dma_channel *channel,
{
struct musb_dma_channel *musb_channel = channel->private_data;
struct musb_dma_controller *controller = musb_channel->controller;
struct musb *musb = controller->private_data;
void __iomem *mbase = controller->base;
u8 bchannel = musb_channel->idx;
u16 csr = 0;
DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
channel, packet_sz, dma_addr, len, mode);
if (mode) {
......@@ -161,7 +162,7 @@ static int dma_channel_program(struct dma_channel *channel,
struct musb_dma_controller *controller = musb_channel->controller;
struct musb *musb = controller->private_data;
DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
musb_channel->epnum,
musb_channel->transmit ? "Tx" : "Rx",
packet_sz, dma_addr, len, mode);
......@@ -274,7 +275,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
#endif
if (!int_hsdma) {
DBG(2, "spurious DMA irq\n");
dev_dbg(musb->controller, "spurious DMA irq\n");
for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
musb_channel = (struct musb_dma_channel *)
......@@ -288,7 +289,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
}
}
DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);
if (!int_hsdma)
goto done;
......@@ -315,7 +316,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
channel->actual_len = addr
- musb_channel->start_addr;
DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
channel, musb_channel->start_addr,
addr, channel->actual_len,
musb_channel->len,
......
......@@ -76,7 +76,7 @@ static void musb_do_idle(unsigned long _musb)
if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
power = musb_readb(musb->mregs, MUSB_POWER);
power &= ~MUSB_POWER_RESUME;
DBG(1, "root port resume stopped, power %02x\n", power);
dev_dbg(musb->controller, "root port resume stopped, power %02x\n", power);
musb_writeb(musb->mregs, MUSB_POWER, power);
musb->is_active = 1;
musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
......@@ -114,7 +114,7 @@ static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || ((musb->a_wait_bcon == 0)
&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
DBG(4, "%s active, deleting timer\n",
dev_dbg(musb->controller, "%s active, deleting timer\n",
otg_state_string(musb->xceiv->state));
del_timer(&musb_idle_timer);
last_timer = jiffies;
......@@ -125,13 +125,13 @@ static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
if (!timer_pending(&musb_idle_timer))
last_timer = timeout;
else {
DBG(4, "Longer idle timer already pending, ignoring\n");
dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
return;
}
}
last_timer = timeout;
DBG(4, "%s inactive, for idle timer for %lu ms\n",
dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
otg_state_string(musb->xceiv->state),
(unsigned long)jiffies_to_msecs(timeout - jiffies));
mod_timer(&musb_idle_timer, timeout);
......@@ -194,7 +194,7 @@ static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
}
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
DBG(1, "VBUS %s, devctl %02x "
dev_dbg(musb->controller, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL));
......@@ -240,7 +240,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
switch (event) {
case USB_EVENT_ID:
DBG(4, "ID GND\n");
dev_dbg(musb->controller, "ID GND\n");
if (is_otg_enabled(musb)) {
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
......@@ -258,7 +258,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
break;
case USB_EVENT_VBUS:
DBG(4, "VBUS Connect\n");
dev_dbg(musb->controller, "VBUS Connect\n");
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
if (musb->gadget_driver)
......@@ -268,7 +268,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
break;
case USB_EVENT_NONE:
DBG(4, "VBUS Disconnect\n");
dev_dbg(musb->controller, "VBUS Disconnect\n");
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
......@@ -286,7 +286,7 @@ static int musb_otg_notifications(struct notifier_block *nb,
otg_shutdown(musb->xceiv);
break;
default:
DBG(4, "ID float\n");
dev_dbg(musb->controller, "ID float\n");
return NOTIFY_DONE;
}
......@@ -340,7 +340,7 @@ static int omap2430_musb_init(struct musb *musb)
status = otg_register_notifier(musb->xceiv, &musb->nb);
if (status)
DBG(1, "notification register failed\n");
dev_dbg(musb->controller, "notification register failed\n");
setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
......
......@@ -106,7 +106,7 @@ static void tusb_wbus_quirk(struct musb *musb, int enabled)
tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
musb_readl(tbase, TUSB_PHY_OTG_CTRL),
musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
} else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
......@@ -115,7 +115,7 @@ static void tusb_wbus_quirk(struct musb *musb, int enabled)
musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
musb_readl(tbase, TUSB_PHY_OTG_CTRL),
musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
phy_otg_ctrl = 0;
......@@ -178,7 +178,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
prefetch(buf);
DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'T', epnum, fifo, len, buf);
if (epnum)
......@@ -225,7 +225,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
void __iomem *fifo = hw_ep->fifo;
u8 epnum = hw_ep->epnum;
DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'R', epnum, fifo, len, buf);
if (epnum)
......@@ -304,7 +304,7 @@ static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
}
musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
DBG(2, "draw max %d mA VBUS\n", mA);
dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
return 0;
}
......@@ -374,7 +374,7 @@ static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
DBG(6, "idle, wake on %02x\n", wakeup_enables);
dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
}
/*
......@@ -421,7 +421,7 @@ static void musb_do_idle(unsigned long _musb)
if ((musb->a_wait_bcon != 0)
&& (musb->idle_timeout == 0
|| time_after(jiffies, musb->idle_timeout))) {
DBG(4, "Nothing connected %s, turning off VBUS\n",
dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
otg_state_string(musb->xceiv->state));
}
/* FALLTHROUGH */
......@@ -481,7 +481,7 @@ static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || ((musb->a_wait_bcon == 0)
&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
DBG(4, "%s active, deleting timer\n",
dev_dbg(musb->controller, "%s active, deleting timer\n",
otg_state_string(musb->xceiv->state));
del_timer(&musb_idle_timer);
last_timer = jiffies;
......@@ -492,13 +492,13 @@ static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
if (!timer_pending(&musb_idle_timer))
last_timer = timeout;
else {
DBG(4, "Longer idle timer already pending, ignoring\n");
dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
return;
}
}
last_timer = timeout;
DBG(4, "%s inactive, for idle timer for %lu ms\n",
dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
otg_state_string(musb->xceiv->state),
(unsigned long)jiffies_to_msecs(timeout - jiffies));
mod_timer(&musb_idle_timer, timeout);
......@@ -573,7 +573,7 @@ static void tusb_musb_set_vbus(struct musb *musb, int is_on)
musb_writel(tbase, TUSB_DEV_CONF, conf);
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL),
musb_readl(tbase, TUSB_DEV_OTG_STAT),
......@@ -634,7 +634,7 @@ static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
#endif
default:
DBG(2, "Trying to set mode %i\n", musb_mode);
dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
return -EINVAL;
}
......@@ -667,7 +667,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
else
default_a = is_host_enabled(musb);
DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
musb->xceiv->default_a = default_a;
tusb_musb_set_vbus(musb, default_a);
......@@ -694,7 +694,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
#endif
if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
DBG(1, "Forcing disconnect (no interrupt)\n");
dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
if (musb->xceiv->state != OTG_STATE_B_IDLE) {
/* INTR_DISCONNECT can hide... */
musb->xceiv->state = OTG_STATE_B_IDLE;
......@@ -702,18 +702,18 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
}
musb->is_active = 0;
}
DBG(2, "vbus change, %s, otg %03x\n",
dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
otg_state_string(musb->xceiv->state), otg_stat);
idle_timeout = jiffies + (1 * HZ);
schedule_work(&musb->irq_work);
} else /* A-dev state machine */ {
DBG(2, "vbus change, %s, otg %03x\n",
dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
otg_state_string(musb->xceiv->state), otg_stat);
switch (musb->xceiv->state) {
case OTG_STATE_A_IDLE:
DBG(2, "Got SRP, turning on VBUS\n");
dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
musb_platform_set_vbus(musb, 1);
/* CONNECT can wake if a_wait_bcon is set */
......@@ -757,7 +757,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
u8 devctl;
DBG(4, "%s timer, %03x\n",
dev_dbg(musb->controller, "%s timer, %03x\n",
otg_state_string(musb->xceiv->state), otg_stat);
switch (musb->xceiv->state) {
......@@ -769,7 +769,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
if ((devctl & MUSB_DEVCTL_VBUS)
!= MUSB_DEVCTL_VBUS) {
DBG(2, "devctl %02x\n", devctl);
dev_dbg(musb->controller, "devctl %02x\n", devctl);
break;
}
musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
......@@ -814,7 +814,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
DBG(3, "TUSB IRQ %08x\n", int_src);
dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
musb->int_usb = (u8) int_src;
......@@ -835,7 +835,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
if (reg == i)
break;
DBG(6, "TUSB NOR not ready\n");
dev_dbg(musb->controller, "TUSB NOR not ready\n");
}
/* work around issue 13 (2nd half) */
......@@ -847,7 +847,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
musb->is_active = 1;
schedule_work(&musb->irq_work);
}
DBG(3, "wake %sactive %02x\n",
dev_dbg(musb->controller, "wake %sactive %02x\n",
musb->is_active ? "" : "in", reg);
/* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
......@@ -869,7 +869,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
DBG(3, "DMA IRQ %08x\n", dma_src);
dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
real_dma_src = ~real_dma_src & dma_src;
if (tusb_dma_omap() && real_dma_src) {
int tx_source = (real_dma_src & 0xffff);
......@@ -877,7 +877,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
for (i = 1; i <= 15; i++) {
if (tx_source & (1 << i)) {
DBG(3, "completing ep%i %s\n", i, "tx");
dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
musb_dma_completion(musb, i, 1);
}
}
......
......@@ -65,7 +65,7 @@ static int tusb_omap_dma_start(struct dma_controller *c)
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
/* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
/* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
return 0;
}
......@@ -76,7 +76,7 @@ static int tusb_omap_dma_stop(struct dma_controller *c)
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
/* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
/* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
return 0;
}
......@@ -89,7 +89,7 @@ static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
if (reg != 0) {
DBG(3, "ep%i dmareq0 is busy for ep%i\n",
dev_dbg(musb->controller, "ep%i dmareq0 is busy for ep%i\n",
chdat->epnum, reg & 0xf);
return -EAGAIN;
}
......@@ -143,7 +143,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
if (ch_status != OMAP_DMA_BLOCK_IRQ)
printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
DBG(3, "ep%i %s dma callback ch: %i status: %x\n",
dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
ch, ch_status);
......@@ -156,7 +156,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
/* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
if (unlikely(remaining > chdat->transfer_len)) {
DBG(2, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
chdat->tx ? "tx" : "rx", chdat->ch,
remaining);
remaining = 0;
......@@ -165,13 +165,13 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
channel->actual_len = chdat->transfer_len - remaining;
pio = chdat->len - channel->actual_len;
DBG(3, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
/* Transfer remaining 1 - 31 bytes */
if (pio > 0 && pio < 32) {
u8 *buf;
DBG(3, "Using PIO for remaining %lu bytes\n", pio);
dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
if (chdat->tx) {
dma_unmap_single(dev, chdat->dma_addr,
......@@ -209,7 +209,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
u16 csr;
if (chdat->tx) {
DBG(3, "terminating short tx packet\n");
dev_dbg(musb->controller, "terminating short tx packet\n");
musb_ep_select(mbase, chdat->epnum);
csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
......@@ -264,7 +264,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
if (dma_remaining) {
DBG(2, "Busy %s dma ch%i, not using: %08x\n",
dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
chdat->tx ? "tx" : "rx", chdat->ch,
dma_remaining);
return false;
......@@ -283,7 +283,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
sync_dev = chdat->sync_dev;
} else {
if (tusb_omap_use_shared_dmareq(chdat) != 0) {
DBG(3, "could not get dma for ep%i\n", chdat->epnum);
dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
return false;
}
if (tusb_dma->ch < 0) {
......@@ -326,7 +326,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
DBG(3, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
ch, dma_addr, chdat->transfer_len, len,
chdat->transfer_packet_sz, packet_sz);
......@@ -370,7 +370,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
}
DBG(3, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
(dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
((dma_addr & 0x3) == 0) ? "sync" : "async",
......@@ -525,7 +525,7 @@ tusb_omap_dma_allocate(struct dma_controller *c,
/* REVISIT: Why does dmareq5 not work? */
if (hw_ep->epnum == 0) {
DBG(3, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
return NULL;
}
......@@ -585,7 +585,7 @@ tusb_omap_dma_allocate(struct dma_controller *c,
chdat->ch = -1;
}
DBG(3, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
chdat->epnum,
chdat->tx ? "tx" : "rx",
chdat->ch >= 0 ? "dedicated" : "shared",
......@@ -598,7 +598,7 @@ tusb_omap_dma_allocate(struct dma_controller *c,
free_dmareq:
tusb_omap_dma_free_dmareq(chdat);
DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum);
dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
channel->status = MUSB_DMA_STATUS_UNKNOWN;
return NULL;
......@@ -611,7 +611,7 @@ static void tusb_omap_dma_release(struct dma_channel *channel)
void __iomem *tbase = musb->ctrl_base;
u32 reg;
DBG(3, "ep%i ch%i\n", chdat->epnum, chdat->ch);
dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch);
reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
if (chdat->tx)
......
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