Commit 5d116999 authored by Feifei Xu's avatar Feifei Xu Committed by Alex Deucher

drm/amdgpu: Correct and simplify sdma 4.x irq.num_types

Correct and init the sdma4.x irq.num_types.

v2: squash in fix (Alex)
Signed-off-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3d2bee91
......@@ -2599,27 +2599,18 @@ static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = {
static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
{
adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
/*For Arcturus and Aldebaran, add another 4 irq handler*/
switch (adev->sdma.num_instances) {
case 1:
adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
break;
case 5:
adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
break;
case 8:
adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
adev->sdma.vm_hole_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
adev->sdma.doorbell_invalid_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
adev->sdma.pool_timeout_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
adev->sdma.srbm_write_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
break;
case 2:
default:
adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
break;
}
adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
......
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