Commit 5d3a0a95 authored by Olof Johansson's avatar Olof Johansson

Merge branch 'next/cleanup2' into HEAD

Conflicts:
	arch/arm/Kconfig
	arch/arm/Makefile
	arch/arm/mach-bcmring/arch.c
	arch/arm/mach-tegra/devices.c
	arch/arm/mach-tegra/dma.c
parents 7e95c548 b98138e0
...@@ -657,22 +657,6 @@ W: http://www.linux4sam.org ...@@ -657,22 +657,6 @@ W: http://www.linux4sam.org
S: Supported S: Supported
F: arch/arm/mach-at91/ F: arch/arm/mach-at91/
ARM/BCMRING ARM ARCHITECTURE
M: Jiandong Zheng <jdzheng@broadcom.com>
M: Scott Branden <sbranden@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-bcmring
ARM/BCMRING MTD NAND DRIVER
M: Jiandong Zheng <jdzheng@broadcom.com>
M: Scott Branden <sbranden@broadcom.com>
L: linux-mtd@lists.infradead.org
S: Maintained
F: drivers/mtd/nand/bcm_umi_nand.c
F: drivers/mtd/nand/bcm_umi_bch.c
F: drivers/mtd/nand/nand_bcm_umi.h
ARM/CALXEDA HIGHBANK ARCHITECTURE ARM/CALXEDA HIGHBANK ARCHITECTURE
M: Rob Herring <rob.herring@calxeda.com> M: Rob Herring <rob.herring@calxeda.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
......
...@@ -364,18 +364,6 @@ config ARCH_BCM2835 ...@@ -364,18 +364,6 @@ config ARCH_BCM2835
This enables support for the Broadcom BCM2835 SoC. This SoC is This enables support for the Broadcom BCM2835 SoC. This SoC is
use in the Raspberry Pi, and Roku 2 devices. use in the Raspberry Pi, and Roku 2 devices.
config ARCH_BCMRING
bool "Broadcom BCMRING"
depends on MMU
select CPU_V6
select ARM_AMBA
select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
help
Support for Broadcom's BCMRing platform.
config ARCH_HIGHBANK config ARCH_HIGHBANK
bool "Calxeda Highbank-based" bool "Calxeda Highbank-based"
select ARCH_WANT_OPTIONAL_GPIOLIB select ARCH_WANT_OPTIONAL_GPIOLIB
...@@ -398,6 +386,8 @@ config ARCH_CLPS711X ...@@ -398,6 +386,8 @@ config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select CPU_ARM720T select CPU_ARM720T
select ARCH_USES_GETTIMEOFFSET select ARCH_USES_GETTIMEOFFSET
select COMMON_CLK
select CLKDEV_LOOKUP
select NEED_MACH_MEMORY_H select NEED_MACH_MEMORY_H
help help
Support for Cirrus Logic 711x/721x/731x based boards. Support for Cirrus Logic 711x/721x/731x based boards.
...@@ -1033,8 +1023,6 @@ source "arch/arm/mach-mvebu/Kconfig" ...@@ -1033,8 +1023,6 @@ source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-at91/Kconfig" source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-bcmring/Kconfig"
source "arch/arm/mach-clps711x/Kconfig" source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig" source "arch/arm/mach-cns3xxx/Kconfig"
......
...@@ -137,7 +137,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 ...@@ -137,7 +137,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
# by CONFIG_* macro name. # by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AT91) := at91 machine-$(CONFIG_ARCH_AT91) := at91
machine-$(CONFIG_ARCH_BCM2835) := bcm2835 machine-$(CONFIG_ARCH_BCM2835) := bcm2835
machine-$(CONFIG_ARCH_BCMRING) := bcmring
machine-$(CONFIG_ARCH_CLPS711X) := clps711x machine-$(CONFIG_ARCH_CLPS711X) := clps711x
machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) := davinci machine-$(CONFIG_ARCH_DAVINCI) := davinci
......
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_EXPERT=y
CONFIG_KALLSYMS_EXTRA_PASS=y
# CONFIG_HOTPLUG is not set
# CONFIG_ELF_CORE is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_BCMRING=y
CONFIG_BCM_ZRELADDR=0x8000
CONFIG_CPU_32v6K=y
CONFIG_NO_HZ=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_ZBOOT_ROM_TEXT=0x0e000000
CONFIG_ZBOOT_ROM_BSS=0x0ea00000
CONFIG_ZBOOT_ROM=y
CONFIG_NET=y
# CONFIG_WIRELESS is not set
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_CFI_I2 is not set
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_VERIFY_WRITE=y
CONFIG_MTD_NAND_BCM_UMI=y
CONFIG_MTD_NAND_BCM_UMI_HWCS=y
# CONFIG_MISC_DEVICES is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_LEGACY_PTY_COUNT=64
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
# CONFIG_JFFS2_FS_SECURITY is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_HEADERS_CHECK=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_ARM_UNWIND is not set
choice
prompt "Processor selection in BCMRING family of devices"
depends on ARCH_BCMRING
default ARCH_BCM11107
config ARCH_FPGA11107
bool "FPGA11107"
config ARCH_BCM11107
bool "BCM11107"
endchoice
menu "BCMRING Options"
depends on ARCH_BCMRING
config BCM_ZRELADDR
hex "Compressed ZREL ADDR"
endmenu
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
obj-y += csp/
# Address where decompressor will be written and eventually executed.
#
# default to SDRAM
zreladdr-y += $(CONFIG_BCM_ZRELADDR)
params_phys-y := 0x00000800
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/sysctl.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/time.h>
#include <asm/mach/arch.h>
#include <mach/dma.h>
#include <mach/hardware.h>
#include <mach/csp/mm_io.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <mach/cfg_global.h>
#include "core.h"
HW_DECLARE_SPINLOCK(arch)
HW_DECLARE_SPINLOCK(gpio)
#if defined(CONFIG_DEBUG_SPINLOCK)
EXPORT_SYMBOL(bcmring_gpio_reg_lock);
#endif
/* sysctl */
static int bcmring_arch_warm_reboot; /* do a warm reboot on hard reset */
static void bcmring_restart(char mode, const char *cmd)
{
printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
if (mode == 'h') {
/* Reboot configured in proc entry */
if (bcmring_arch_warm_reboot) {
printk("warm reset\n");
/* Issue Warm reset (do not reset ethernet switch, keep alive) */
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
} else {
/* Force reset of everything */
printk("force reset\n");
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
} else {
/* Force reset of everything */
printk("force reset\n");
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
}
static struct ctl_table_header *bcmring_sysctl_header;
static struct ctl_table bcmring_sysctl_warm_reboot[] = {
{
.procname = "warm",
.data = &bcmring_arch_warm_reboot,
.maxlen = sizeof(int),
.mode = 0644,
.proc_handler = proc_dointvec},
{}
};
static struct ctl_table bcmring_sysctl_reboot[] = {
{
.procname = "reboot",
.mode = 0555,
.child = bcmring_sysctl_warm_reboot},
{}
};
static struct resource nand_resource[] = {
[0] = {
.start = MM_ADDR_IO_NAND,
.end = MM_ADDR_IO_NAND + 0x1000 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device nand_device = {
.name = "bcm-nand",
.id = -1,
.resource = nand_resource,
.num_resources = ARRAY_SIZE(nand_resource),
};
static struct resource pmu_resource = {
.start = IRQ_PMUIRQ,
.end = IRQ_PMUIRQ,
.flags = IORESOURCE_IRQ,
};
static struct platform_device pmu_device = {
.name = "arm-pmu",
.id = -1,
.resource = &pmu_resource,
.num_resources = 1,
};
static struct platform_device *devices[] __initdata = {
&nand_device,
&pmu_device,
};
/****************************************************************************
*
* Called from the customize_machine function in arch/arm/kernel/setup.c
*
* The customize_machine function is tagged as an arch_initcall
* (see include/linux/init.h for the order that the various init sections
* are called in.
*
*****************************************************************************/
static void __init bcmring_init_machine(void)
{
bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
/* Enable spread spectrum */
chipcHw_enableSpreadSpectrum();
platform_add_devices(devices, ARRAY_SIZE(devices));
bcmring_amba_init();
dma_init();
}
/****************************************************************************
*
* Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
* passed in by the boot loader.
*
*****************************************************************************/
static void __init bcmring_fixup(struct tag *t, char **cmdline,
struct meminfo *mi) {
#ifdef CONFIG_BLK_DEV_INITRD
printk(KERN_NOTICE "bcmring_fixup\n");
t->hdr.tag = ATAG_CORE;
t->hdr.size = tag_size(tag_core);
t->u.core.flags = 0;
t->u.core.pagesize = PAGE_SIZE;
t->u.core.rootdev = 31 << 8 | 0;
t = tag_next(t);
t->hdr.tag = ATAG_MEM;
t->hdr.size = tag_size(tag_mem32);
t->u.mem.start = CFG_GLOBAL_RAM_BASE;
t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
t = tag_next(t);
t->hdr.tag = ATAG_NONE;
t->hdr.size = 0;
#endif
}
/****************************************************************************
*
* Machine Description
*
*****************************************************************************/
MACHINE_START(BCMRING, "BCMRING")
/* Maintainer: Broadcom Corporation */
.fixup = bcmring_fixup,
.map_io = bcmring_map_io,
.init_early = bcmring_init_early,
.init_irq = bcmring_init_irq,
.timer = &bcmring_timer,
.init_machine = bcmring_init_machine,
.restart = bcmring_restart,
MACHINE_END
/*****************************************************************************
* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/clkdev.h>
#include <mach/csp/hw_cfg.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_reg.h>
#include <mach/csp/chipcHw_inline.h>
#include "clock.h"
#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
#define clk_is_pll1(x) ((x)->type & CLK_TYPE_PLL1)
#define clk_is_pll2(x) ((x)->type & CLK_TYPE_PLL2)
#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
#define clk_is_bypassable(x) ((x)->type & CLK_TYPE_BYPASSABLE)
#define clk_is_using_xtal(x) ((x)->mode & CLK_MODE_XTAL)
static DEFINE_SPINLOCK(clk_lock);
static void __clk_enable(struct clk *clk)
{
if (!clk)
return;
/* enable parent clock first */
if (clk->parent)
__clk_enable(clk->parent);
if (clk->use_cnt++ == 0) {
if (clk_is_pll1(clk)) { /* PLL1 */
chipcHw_pll1Enable(clk->rate_hz, 0);
} else if (clk_is_pll2(clk)) { /* PLL2 */
chipcHw_pll2Enable(clk->rate_hz);
} else if (clk_is_using_xtal(clk)) { /* source is crystal */
if (!clk_is_primary(clk))
chipcHw_bypassClockEnable(clk->csp_id);
} else { /* source is PLL */
chipcHw_setClockEnable(clk->csp_id);
}
}
}
int clk_enable(struct clk *clk)
{
unsigned long flags;
if (!clk)
return -EINVAL;
spin_lock_irqsave(&clk_lock, flags);
__clk_enable(clk);
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_enable);
static void __clk_disable(struct clk *clk)
{
if (!clk)
return;
BUG_ON(clk->use_cnt == 0);
if (--clk->use_cnt == 0) {
if (clk_is_pll1(clk)) { /* PLL1 */
chipcHw_pll1Disable();
} else if (clk_is_pll2(clk)) { /* PLL2 */
chipcHw_pll2Disable();
} else if (clk_is_using_xtal(clk)) { /* source is crystal */
if (!clk_is_primary(clk))
chipcHw_bypassClockDisable(clk->csp_id);
} else { /* source is PLL */
chipcHw_setClockDisable(clk->csp_id);
}
}
if (clk->parent)
__clk_disable(clk->parent);
}
void clk_disable(struct clk *clk)
{
unsigned long flags;
if (!clk)
return;
spin_lock_irqsave(&clk_lock, flags);
__clk_disable(clk);
spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0;
return clk->rate_hz;
}
EXPORT_SYMBOL(clk_get_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
unsigned long actual;
unsigned long rate_hz;
if (!clk)
return -EINVAL;
if (!clk_is_programmable(clk))
return -EINVAL;
if (clk->use_cnt)
return -EBUSY;
spin_lock_irqsave(&clk_lock, flags);
actual = clk->parent->rate_hz;
rate_hz = min(actual, rate);
spin_unlock_irqrestore(&clk_lock, flags);
return rate_hz;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
unsigned long actual;
unsigned long rate_hz;
if (!clk)
return -EINVAL;
if (!clk_is_programmable(clk))
return -EINVAL;
if (clk->use_cnt)
return -EBUSY;
spin_lock_irqsave(&clk_lock, flags);
actual = clk->parent->rate_hz;
rate_hz = min(actual, rate);
rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
clk->rate_hz = rate_hz;
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_set_rate);
struct clk *clk_get_parent(struct clk *clk)
{
if (!clk)
return NULL;
return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
unsigned long flags;
struct clk *old_parent;
if (!clk || !parent)
return -EINVAL;
if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
return -EINVAL;
/* if more than one user, parent is not allowed */
if (clk->use_cnt > 1)
return -EBUSY;
if (clk->parent == parent)
return 0;
spin_lock_irqsave(&clk_lock, flags);
old_parent = clk->parent;
clk->parent = parent;
if (clk_is_using_xtal(parent))
clk->mode |= CLK_MODE_XTAL;
else
clk->mode &= (~CLK_MODE_XTAL);
/* if clock is active */
if (clk->use_cnt != 0) {
clk->use_cnt--;
/* enable clock with the new parent */
__clk_enable(clk);
/* disable the old parent */
__clk_disable(old_parent);
}
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
/*****************************************************************************
* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <mach/csp/chipcHw_def.h>
#define CLK_TYPE_PRIMARY 1 /* primary clock must NOT have a parent */
#define CLK_TYPE_PLL1 2 /* PPL1 */
#define CLK_TYPE_PLL2 4 /* PPL2 */
#define CLK_TYPE_PROGRAMMABLE 8 /* programmable clock rate */
#define CLK_TYPE_BYPASSABLE 16 /* parent can be changed */
#define CLK_MODE_XTAL 1 /* clock source is from crystal */
struct clk {
const char *name; /* clock name */
unsigned int type; /* clock type */
unsigned int mode; /* current mode */
volatile int use_bypass; /* indicate if it's in bypass mode */
chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */
unsigned long rate_hz; /* clock rate in Hz */
unsigned int use_cnt; /* usage count */
struct clk *parent; /* parent clock */
};
/*
* derived from linux/arch/arm/mach-versatile/core.c
* linux/arch/arm/mach-bcmring/core.c
*
* Copyright (C) 1999 - 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* Portions copyright Broadcom 2008 */
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/clkdev.h>
#include <mach/csp/mm_addr.h>
#include <mach/hardware.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/cfg_global.h>
#include "clock.h"
#include <mach/csp/secHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <mach/csp/tmrHw_reg.h>
static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
static struct clk pll1_clk = {
.name = "PLL1",
.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
.rate_hz = 2000000000,
.use_cnt = 7,
};
static struct clk uart_clk = {
.name = "UART",
.type = CLK_TYPE_PROGRAMMABLE,
.csp_id = chipcHw_CLOCK_UART,
.rate_hz = HW_CFG_UART_CLK_HZ,
.parent = &pll1_clk,
};
static struct clk dummy_apb_pclk = {
.name = "BUSCLK",
.type = CLK_TYPE_PRIMARY,
.mode = CLK_MODE_XTAL,
};
/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
#if defined(CONFIG_ARCH_FPGA11107)
/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
/* slow down Linux's sense of time */
#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
#else
#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
#endif
static struct clk sp804_timer012_clk = {
.name = "sp804-timer-0,1,2",
.type = CLK_TYPE_PRIMARY,
.mode = CLK_MODE_XTAL,
.rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
};
static struct clk sp804_timer3_clk = {
.name = "sp804-timer-3",
.type = CLK_TYPE_PRIMARY,
.mode = CLK_MODE_XTAL,
.rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
};
static struct clk_lookup lookups[] = {
{ /* Bus clock */
.con_id = "apb_pclk",
.clk = &dummy_apb_pclk,
}, { /* UART0 */
.dev_id = "uarta",
.clk = &uart_clk,
}, { /* UART1 */
.dev_id = "uartb",
.clk = &uart_clk,
}, { /* SP804 timer 0 */
.dev_id = "sp804",
.con_id = "timer0",
.clk = &sp804_timer012_clk,
}, { /* SP804 timer 1 */
.dev_id = "sp804",
.con_id = "timer1",
.clk = &sp804_timer012_clk,
}, { /* SP804 timer 3 */
.dev_id = "sp804",
.con_id = "timer3",
.clk = &sp804_timer3_clk,
}
};
static struct amba_device *amba_devs[] __initdata = {
&uartA_device,
&uartB_device,
};
void __init bcmring_amba_init(void)
{
int i;
u32 bus_clock;
/* Linux is run initially in non-secure mode. Secure peripherals */
/* generate FIQ, and must be handled in secure mode. Until we have */
/* a linux security monitor implementation, keep everything in */
/* non-secure mode. */
chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
secHw_BLK_MASK_KEY_SCAN |
secHw_BLK_MASK_TOUCH_SCREEN |
secHw_BLK_MASK_UART0 |
secHw_BLK_MASK_UART1 |
secHw_BLK_MASK_WATCHDOG |
secHw_BLK_MASK_SPUM |
secHw_BLK_MASK_DDR2 |
secHw_BLK_MASK_SPU |
secHw_BLK_MASK_PKA |
secHw_BLK_MASK_RNG |
secHw_BLK_MASK_RTC |
secHw_BLK_MASK_OTP |
secHw_BLK_MASK_BOOT |
secHw_BLK_MASK_MPU |
secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
/* Only the devices attached to the AMBA bus are enabled just before the bus is */
/* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
/* driver to access these blocks. The bus is probed, and the drivers are loaded. */
/* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
bus_clock = chipcHw_REG_BUS_CLOCK_GE
| chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
chipcHw_busInterfaceClockEnable(bus_clock);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
}
/*
* Where is the timer (VA)?
*/
#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR)
#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
static int __init bcmring_clocksource_init(void)
{
/* setup timer1 as free-running clocksource */
sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
/* setup timer3 as free-running clocksource */
sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
return 0;
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
void __init bcmring_init_timer(void)
{
printk(KERN_INFO "bcmring_init_timer\n");
/*
* Initialise to a known state (all timers off)
*/
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
/*
* Make irqs happen for the system timer
*/
bcmring_clocksource_init();
sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
}
struct sys_timer bcmring_timer = {
.init = bcmring_init_timer,
};
void __init bcmring_init_early(void)
{
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
}
/*
* linux/arch/arm/mach-versatile/core.h
*
* Copyright (C) 2004 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* Portions copyright Broadcom 2008 */
#ifndef __ASM_ARCH_BCMRING_H
#define __ASM_ARCH_BCMRING_H
void __init bcmring_amba_init(void);
void __init bcmring_map_io(void);
void __init bcmring_init_irq(void);
void __init bcmring_init_early(void);
extern struct sys_timer bcmring_timer;
#endif
obj-y += dmac/
obj-y += tmr/
obj-y += chipc/
obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
This diff is collapsed.
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file chipcHw_init.c
*
* @brief Low level CHIPC PLL configuration functions
*
* @note
*
* These routines provide basic PLL controlling functionality only.
*/
/****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/export.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <mach/csp/reg.h>
#include <linux/delay.h>
/* ---- Private Constants and Types --------------------------------------- */
/*
Calculation for NDIV_i to obtain VCO frequency
-----------------------------------------------
Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
for Freq_vco = VCO_FREQ_MHz
Freq_ref = chipcHw_XTAL_FREQ_Hz
PLL_P1 = PLL_P2 = 1
and
PLL_NDIV_f = 0
We get:
PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
Calculation for PLL MDIV to obtain frequency Freq_x for channel x
-----------------------------------------------------------------
Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
*/
/* ---- Private Variables ------------------------------------------------- */
/****************************************************************************/
/**
* @brief Initializes the PLL2
*
* This function initializes the PLL2
*
*/
/****************************************************************************/
void chipcHw_pll2Enable(uint32_t vcoFreqHz)
{
uint32_t pllPreDivider2 = 0;
{
REG_LOCAL_IRQ_SAVE;
writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET,
&pChipcHw->PLLConfig2);
pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
(chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P1 <<
chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P2 <<
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
/* Enable CHIPC registers to control the PLL */
writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
/* Set pre divider to get desired VCO frequency */
writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
/* Set NDIV Frac */
writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);
/* This has to be removed once the default values are fixed for PLL2. */
writel(0x38000700, &pChipcHw->PLLControl12);
writel(0x00000015, &pChipcHw->PLLControl22);
/* Reset PLL2 */
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN,
&pChipcHw->PLLConfig2);
} else {
writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN,
&pChipcHw->PLLConfig2);
}
REG_LOCAL_IRQ_RESTORE;
}
/* Insert certain amount of delay before deasserting ARESET. */
udelay(1);
{
REG_LOCAL_IRQ_SAVE;
/* Remove analog reset and Power on the PLL */
writel(readl(&pChipcHw->PLLConfig2) &
~(chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_POWER_DOWN),
&pChipcHw->PLLConfig2);
REG_LOCAL_IRQ_RESTORE;
}
/* Wait until PLL is locked */
while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
;
{
REG_LOCAL_IRQ_SAVE;
/* Remove digital reset */
writel(readl(&pChipcHw->PLLConfig2) &
~chipcHw_REG_PLL_CONFIG_D_RESET,
&pChipcHw->PLLConfig2);
REG_LOCAL_IRQ_RESTORE;
}
}
EXPORT_SYMBOL(chipcHw_pll2Enable);
/****************************************************************************/
/**
* @brief Initializes the PLL1
*
* This function initializes the PLL1
*
*/
/****************************************************************************/
void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
{
uint32_t pllPreDivider = 0;
{
REG_LOCAL_IRQ_SAVE;
writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET,
&pChipcHw->PLLConfig);
/* Setting VCO frequency */
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
pllPreDivider =
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P1 <<
chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P2 <<
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
} else {
pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
(chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P1 <<
chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P2 <<
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
}
/* Enable CHIPC registers to control the PLL */
writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
/* Set pre divider to get desired VCO frequency */
writel(pllPreDivider, &pChipcHw->PLLPreDivider);
/* Set NDIV Frac */
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
} else {
writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
}
/* Reset PLL1 */
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
} else {
writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
}
REG_LOCAL_IRQ_RESTORE;
/* Insert certain amount of delay before deasserting ARESET. */
udelay(1);
{
REG_LOCAL_IRQ_SAVE;
/* Remove analog reset and Power on the PLL */
writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
REG_LOCAL_IRQ_RESTORE;
}
/* Wait until PLL is locked */
while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
|| !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
;
/* Remove digital reset */
{
REG_LOCAL_IRQ_SAVE;
writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
REG_LOCAL_IRQ_RESTORE;
}
}
}
EXPORT_SYMBOL(chipcHw_pll1Enable);
/****************************************************************************/
/**
* @brief Initializes the chipc module
*
* This function initializes the PLLs and core system clocks
*
*/
/****************************************************************************/
void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */
) {
#if !(defined(__KERNEL__) && !defined(STANDALONE))
delay_init();
#endif
/* Do not program PLL, when warm reset */
if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
chipcHw_pll1Enable(initParam->pllVcoFreqHz,
initParam->ssSupport);
chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
} else {
/* Clear sticky bits */
chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
}
/* Clear sticky bits */
chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
/* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);
/* Set various core component frequencies. The order in which this is done is important for some. */
/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
/* frequency to find its ratio with the BUS. Hence we must set the ARM first, followed by the BUS, */
/* then VPM and RTBUS. */
chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
initParam->busClockFreqHz *
initParam->armBusRatio);
chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
initParam->busClockFreqHz *
initParam->vpmBusRatio);
chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
initParam->busClockFreqHz *
initParam->ddrBusRatio);
chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
initParam->busClockFreqHz / 2);
}
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
#include <linux/types.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <mach/csp/intcHw_reg.h>
#include <asm/cacheflush.h>
/* ---- Private Constants and Types --------------------------------------- */
/* ---- Private Variables ------------------------------------------------- */
void chipcHw_reset_run_from_aram(void);
typedef void (*RUNFUNC) (void);
/****************************************************************************/
/**
* @brief warmReset
*
* @note warmReset configures the clocks which are not reset back to the state
* required to execute on reset. To do so we need to copy the code into internal
* memory to change the ARM clock while we are not executing from DDR.
*/
/****************************************************************************/
void chipcHw_reset(uint32_t mask)
{
int i = 0;
RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
/* Disable all interrupts */
intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
{
REG_LOCAL_IRQ_SAVE;
if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
/* Bypass the PLL clocks before reboot */
writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
&pChipcHw->UARTClock);
writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
&pChipcHw->SPIClock);
/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
do {
writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
i++;
} while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
flush_cache_all();
/* run the function from ARAM */
runFunc();
/* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
REG_LOCAL_IRQ_RESTORE;
}
}
/* This function must run from internal memory */
void chipcHw_reset_run_from_aram(void)
{
/* Make sure, pipeline is filled with instructions coming from ARAM */
__asm (" nop \n\t"
" nop \n\t"
#if defined(__KERNEL__) && !defined(STANDALONE)
" MRC p15,#0x0,r0,c1,c0,#0 \n\t"
" BIC r0,r0,#0xd \n\t"
" MCR p15,#0x0,r0,c1,c0,#0 \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
#endif
" nop \n\t"
" nop \n\t"
/* Bypass the ARM clock and switch to XTAL clock */
" MOV r2,#0x80000000 \n\t"
" LDR r3,[r2,#8] \n\t"
" ORR r3,r3,#0x20000 \n\t"
" STR r3,[r2,#8] \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
/* Issue reset */
" MOV r3,#0x2 \n\t"
" STR r3,[r2,#0x80] \n\t"
/* End here */
" MOV pc,pc \n\t");
/* 0xe1a0f00f == asm ("mov r15, r15"); */
}
/*****************************************************************************
* Copyright 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file chipcHw_str.c
*
* @brief Contains strings which are useful to linux and csp
*
* @note
*/
/****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
#include <mach/csp/chipcHw_inline.h>
/* ---- Private Constants and Types --------------------------------------- */
static const char *gMuxStr[] = {
"GPIO", /* 0 */
"KeyPad", /* 1 */
"I2C-Host", /* 2 */
"SPI", /* 3 */
"Uart", /* 4 */
"LED-Mtx-P", /* 5 */
"LED-Mtx-S", /* 6 */
"SDIO-0", /* 7 */
"SDIO-1", /* 8 */
"PCM", /* 9 */
"I2S", /* 10 */
"ETM", /* 11 */
"Debug", /* 12 */
"Misc", /* 13 */
"0xE", /* 14 */
"0xF", /* 15 */
};
/****************************************************************************/
/**
* @brief Retrieves a string representation of the mux setting for a pin.
*
* @return Pointer to a character string.
*/
/****************************************************************************/
const char *chipcHw_getGpioPinFunctionStr(int pin)
{
if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
return "";
}
return gMuxStr[chipcHw_getGpioPinFunction(pin)];
}
obj-y += dmacHw.o dmacHw_extra.o
\ No newline at end of file
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
/*****************************************************************************
* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CFG_GLOBAL_DEFINES_H
#define CFG_GLOBAL_DEFINES_H
/* CHIP */
#define BCM1103 1
#define BCM1191 4
#define BCM2153 5
#define BCM2820 6
#define BCM2826 8
#define FPGA11107 9
#define BCM11107 10
#define BCM11109 11
#define BCM11170 12
#define BCM11110 13
#define BCM11211 14
/* CFG_GLOBAL_CHIP_FAMILY types */
#define CFG_GLOBAL_CHIP_FAMILY_NONE 0
#define CFG_GLOBAL_CHIP_FAMILY_BCM116X 2
#define CFG_GLOBAL_CHIP_FAMILY_BCMRING 4
#define CFG_GLOBAL_CHIP_FAMILY_BCM1103 8
#define IMAGE_HEADER_SIZE_CHECKSUM 4
#endif
#ifndef _CFG_GLOBAL_H_
#define _CFG_GLOBAL_H_
#define CFG_GLOBAL_CHIP BCM11107
#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING
#define CFG_GLOBAL_CHIP_REV 0xB0
#define CFG_GLOBAL_RAM_SIZE 0x10000000
#define CFG_GLOBAL_RAM_BASE 0x00000000
#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000
#endif /* _CFG_GLOBAL_H_ */
/*****************************************************************************
* Copyright 2009 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CAP_H
#define CAP_H
/* ---- Include Files ---------------------------------------------------- */
/* ---- Public Constants and Types --------------------------------------- */
typedef enum {
CAP_NOT_PRESENT = 0,
CAP_PRESENT
} CAP_RC_T;
typedef enum {
CAP_VPM,
CAP_ETH_PHY,
CAP_ETH_GMII,
CAP_ETH_SGMII,
CAP_USB,
CAP_TSC,
CAP_EHSS,
CAP_SDIO,
CAP_UARTB,
CAP_KEYPAD,
CAP_CLCD,
CAP_GE,
CAP_LEDM,
CAP_BBL,
CAP_VDEC,
CAP_PIF,
CAP_APM,
CAP_SPU,
CAP_PKA,
CAP_RNG,
} CAP_CAPABILITY_T;
typedef enum {
CAP_LCD_WVGA = 0,
CAP_LCD_VGA = 0x1,
CAP_LCD_WQVGA = 0x2,
CAP_LCD_QVGA = 0x3
} CAP_LCD_RES_T;
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index);
static inline uint32_t cap_getMaxArmSpeedHz(void);
static inline uint32_t cap_getMaxVpmSpeedHz(void);
static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
#endif
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file dmacHw_priv.h
*
* @brief Private Definitions for low level DMA driver
*
*/
/****************************************************************************/
#ifndef _DMACHW_PRIV_H
#define _DMACHW_PRIV_H
#include <linux/types.h>
/* Data type for DMA Link List Item */
typedef struct {
uint32_t sar; /* Source Address Register.
Address must be aligned to CTLx.SRC_TR_WIDTH. */
uint32_t dar; /* Destination Address Register.
Address must be aligned to CTLx.DST_TR_WIDTH. */
uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
Address MUST be aligned to a 32-bit boundary. */
dmacHw_REG64_t ctl; /* Control Register. 64 bits */
uint32_t sstat; /* Source Status Register */
uint32_t dstat; /* Destination Status Register */
uint32_t devCtl; /* Device specific control information */
uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
} dmacHw_DESC_t;
/*
* Descriptor ring pointers
*/
typedef struct {
int num; /* Number of link items */
dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */
dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */
dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */
dmacHw_DESC_t *pEnd; /* End of current descriptor chain */
dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */
uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */
} dmacHw_DESC_RING_t;
/*
* DMA channel control block
*/
typedef struct {
uint32_t module; /* DMA controller module (0-1) */
uint32_t channel; /* DMA channel (0-7) */
volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */
volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */
void *userData; /* Channel specifc user data */
} dmacHw_CBLK_t;
#define dmacHw_ASSERT(a) if (!(a)) while (1)
#define dmacHw_MAX_CHANNEL_COUNT 16
#define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF
#define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE
#define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF)
#define dmacHw_MAX_BLOCKSIZE 4064
#define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr)
#define dmacHw_ADDRESS_MASK(byte) ((byte) - 1)
#define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
#define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle))
#define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp))
#define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
/****************************************************************************/
/**
* @brief Get next available transaction width
*
*
* @return On success : Next available transaction width
* On failure : dmacHw_TRANSACTION_WIDTH_8
*
* @note
* None
*/
/****************************************************************************/
static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */
) {
if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
} else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
}
/* Default return */
return dmacHw_SRC_TRANSACTION_WIDTH_8;
}
/****************************************************************************/
/**
* @brief Get number of bytes per transaction
*
* @return Number of bytes per transaction
*
*
* @note
* None
*/
/****************************************************************************/
static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */
) {
int width = 1;
switch (tw) {
case dmacHw_SRC_TRANSACTION_WIDTH_8:
width = 1;
break;
case dmacHw_SRC_TRANSACTION_WIDTH_16:
case dmacHw_DST_TRANSACTION_WIDTH_16:
width = 2;
break;
case dmacHw_SRC_TRANSACTION_WIDTH_32:
case dmacHw_DST_TRANSACTION_WIDTH_32:
width = 4;
break;
case dmacHw_SRC_TRANSACTION_WIDTH_64:
case dmacHw_DST_TRANSACTION_WIDTH_64:
width = 8;
break;
default:
dmacHw_ASSERT(0);
}
/* Default transaction width */
return width;
}
#endif /* _DMACHW_PRIV_H */
This diff is collapsed.
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_HW_CFG_H
#define CSP_HW_CFG_H
/* ---- Include Files ---------------------------------------------------- */
#include <mach/cfg_global.h>
#include <mach/csp/cap_inline.h>
#if defined(__KERNEL__)
#include <mach/memory_settings.h>
#else
#include <hw_cfg.h>
#endif
/* Some items that can be defined externally, but will be set to default values */
/* if they are not defined. */
/* HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE Default undefined and SS is enabled. */
/* HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
/* HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
/* HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
/* HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
/* HW_CFG_SDRAM_ADDR_BRC Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
/* HW_CFG_SDRAM_CLK_ASYNC Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
#if defined(CFG_GLOBAL_CHIP)
#if (CFG_GLOBAL_CHIP == FPGA11107)
#define HW_CFG_BUS_CLK_HZ 5000000
#define HW_CFG_DDR_CTLR_CLK_HZ 10000000
#define HW_CFG_DDR_PHY_OMIT
#define HW_CFG_UART_CLK_HZ 7500000
#else
#define HW_CFG_PLL_VCO_HZ 2000000000
#define HW_CFG_PLL2_VCO_HZ 1800000000
#define HW_CFG_ARM_CLK_HZ CAP_HW_CFG_ARM_CLK_HZ
#define HW_CFG_BUS_CLK_HZ 166666666
#define HW_CFG_DDR_CTLR_CLK_HZ 333333333
#define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
#define HW_CFG_UART_CLK_HZ 142857142
#define HW_CFG_VPM_CLK_HZ CAP_HW_CFG_VPM_CLK_HZ
#endif
#else
#define HW_CFG_PLL_VCO_HZ 1800000000
#define HW_CFG_PLL2_VCO_HZ 1800000000
#define HW_CFG_ARM_CLK_HZ 450000000
#define HW_CFG_BUS_CLK_HZ 150000000
#define HW_CFG_DDR_CTLR_CLK_HZ 300000000
#define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
#define HW_CFG_UART_CLK_HZ 150000000
#define HW_CFG_VPM_CLK_HZ 300000000
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_HW_CFG_H */
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
...@@ -16,12 +16,6 @@ config ARCH_CDB89712 ...@@ -16,12 +16,6 @@ config ARCH_CDB89712
The board includes 2 serial ports, Ethernet, IRDA, and expansion The board includes 2 serial ports, Ethernet, IRDA, and expansion
headers. It comes with 16 MB SDRAM and 8 MB flash ROM. headers. It comes with 16 MB SDRAM and 8 MB flash ROM.
config ARCH_CEIVA
bool "CEIVA"
help
Say Y here if you intend to run this kernel on the Ceiva/Polaroid
PhotoMax Digital Picture Frame.
config ARCH_CLEP7312 config ARCH_CLEP7312
bool "CLEP7312" bool "CLEP7312"
help help
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment