Commit 5d5b43f5 authored by Pierre Moreau's avatar Pierre Moreau Committed by Ben Skeggs

drm/nouveau/pci: Handle 5-bit and 8-bit tag field

If the hardware supports extended tag field (8-bit ones), then enable it.

This is usually done by the VBIOS, but not on some MBPs (see fdo#86537).

In case extended tag field is not supported, 5-bit tag field is used which
limits the possible number of requests to 32. Apparently bits 7:0 of
0x08841c stores some number of outstanding requests, so cap it to 32 if
extended tag is unsupported.

Fixes: fdo#86537

v2: Restrict changes to chipsets >= 0x84
v3:
  * Add nvkm_pci_mask to pci.h
  * Mask bit 8 before setting it
v4:
  * Rename `add` argument of nvkm_pci_mask to `value`
  * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset
    checks
v5:
  * Rebase code on latest PCI structure
  * Restore PCIe check
  * Fix namings in nvkm_pci_mask
  * Rephrase part of the commit message
Signed-off-by: default avatarPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 354a2249
...@@ -24,6 +24,7 @@ struct nvkm_pci { ...@@ -24,6 +24,7 @@ struct nvkm_pci {
u32 nvkm_pci_rd32(struct nvkm_pci *, u16 addr); u32 nvkm_pci_rd32(struct nvkm_pci *, u16 addr);
void nvkm_pci_wr08(struct nvkm_pci *, u16 addr, u8 data); void nvkm_pci_wr08(struct nvkm_pci *, u16 addr, u8 data);
void nvkm_pci_wr32(struct nvkm_pci *, u16 addr, u32 data); void nvkm_pci_wr32(struct nvkm_pci *, u16 addr, u32 data);
u32 nvkm_pci_mask(struct nvkm_pci *, u16 addr, u32 mask, u32 value);
void nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow); void nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow);
int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
......
...@@ -46,6 +46,14 @@ nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data) ...@@ -46,6 +46,14 @@ nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data)
pci->func->wr32(pci, addr, data); pci->func->wr32(pci, addr, data);
} }
u32
nvkm_pci_mask(struct nvkm_pci *pci, u16 addr, u32 mask, u32 value)
{
u32 data = pci->func->rd32(pci, addr);
pci->func->wr32(pci, addr, (data & ~mask) | value);
return data;
}
void void
nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow) nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow)
{ {
......
...@@ -25,8 +25,32 @@ ...@@ -25,8 +25,32 @@
#include <core/pci.h> #include <core/pci.h>
void
g84_pci_init(struct nvkm_pci *pci)
{
/* The following only concerns PCIe cards. */
if (!pci_is_pcie(pci->pdev))
return;
/* Tag field is 8-bit long, regardless of EXT_TAG.
* However, if EXT_TAG is disabled, only the lower 5 bits of the tag
* field should be used, limiting the number of request to 32.
*
* Apparently, 0x041c stores some limit on the number of requests
* possible, so if EXT_TAG is disabled, limit that requests number to
* 32
*
* Fixes fdo#86537
*/
if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020)
nvkm_pci_mask(pci, 0x0080, 0x00000100, 0x00000100);
else
nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000);
}
static const struct nvkm_pci_func static const struct nvkm_pci_func
g84_pci_func = { g84_pci_func = {
.init = g84_pci_init,
.rd32 = nv40_pci_rd32, .rd32 = nv40_pci_rd32,
.wr08 = nv40_pci_wr08, .wr08 = nv40_pci_wr08,
.wr32 = nv40_pci_wr32, .wr32 = nv40_pci_wr32,
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
static const struct nvkm_pci_func static const struct nvkm_pci_func
g94_pci_func = { g94_pci_func = {
.init = g84_pci_init,
.rd32 = nv40_pci_rd32, .rd32 = nv40_pci_rd32,
.wr08 = nv40_pci_wr08, .wr08 = nv40_pci_wr08,
.wr32 = nv40_pci_wr32, .wr32 = nv40_pci_wr32,
......
...@@ -31,6 +31,7 @@ gf100_pci_msi_rearm(struct nvkm_pci *pci) ...@@ -31,6 +31,7 @@ gf100_pci_msi_rearm(struct nvkm_pci *pci)
static const struct nvkm_pci_func static const struct nvkm_pci_func
gf100_pci_func = { gf100_pci_func = {
.init = g84_pci_init,
.rd32 = nv40_pci_rd32, .rd32 = nv40_pci_rd32,
.wr08 = nv40_pci_wr08, .wr08 = nv40_pci_wr08,
.wr32 = nv40_pci_wr32, .wr32 = nv40_pci_wr32,
......
...@@ -20,4 +20,6 @@ void nv40_pci_wr32(struct nvkm_pci *, u16, u32); ...@@ -20,4 +20,6 @@ void nv40_pci_wr32(struct nvkm_pci *, u16, u32);
void nv40_pci_msi_rearm(struct nvkm_pci *); void nv40_pci_msi_rearm(struct nvkm_pci *);
void nv46_pci_msi_rearm(struct nvkm_pci *); void nv46_pci_msi_rearm(struct nvkm_pci *);
void g84_pci_init(struct nvkm_pci *pci);
#endif #endif
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