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Commit 5df33a62 authored by Viresh Kumar's avatar Viresh Kumar Committed by Arnd Bergmann
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SPEAr: Switch to common clock framework 

SPEAr SoCs used its own clock framework since now. From now on they will move to
use common clock framework.

This patch updates existing SPEAr machine support to adapt for common clock
framework.
Signed-off-by: default avatarViresh Kumar <viresh.kumar@st.com>
Reviewed-by: default avatarMike Turquette <mturquette@linaro.org>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
parent f8abc080
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MAINTAINERS
View file @ 5df33a62
......@@ -6336,9 +6336,7 @@ L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
S: Maintained
F: arch/arm/mach-spear*/clock.c
F: arch/arm/plat-spear/clock.c
F: arch/arm/plat-spear/include/plat/clock.h
F: drivers/clk/spear/
SPEAR PAD MULTIPLEXING SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
......
arch/arm/Kconfig
View file @ 5df33a62
......@@ -980,6 +980,7 @@ config PLAT_SPEAR
select ARM_AMBA
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select COMMON_CLK
select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
select HAVE_CLK
......
arch/arm/mach-spear3xx/Makefile
View file @ 5df33a62
......@@ -3,7 +3,7 @@
#
# common files
obj-y += spear3xx.o clock.o
obj-y += spear3xx.o
# spear300 specific files
obj-$(CONFIG_MACH_SPEAR300) += spear300.o
......
arch/arm/mach-spear3xx/clock.c deleted 100644 → 0
View file @ f8abc080
This diff is collapsed.
arch/arm/mach-spear3xx/include/mach/generic.h
View file @ 5df33a62
......@@ -36,8 +36,8 @@ extern struct amba_device spear3xx_uart_device;
extern struct sys_timer spear3xx_timer;
/* Add spear3xx family function declarations here */
void __init spear3xx_clk_init(void);
void __init spear_setup_timer(void);
void __init spear3xx_clk_init(void);
void __init spear3xx_map_io(void);
void __init spear3xx_init_irq(void);
void __init spear3xx_init(void);
......@@ -156,7 +156,6 @@ extern struct pmx_dev spear310_pmx_tdm0;
/* Add spear310 machine function declarations here */
void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR310 */
/* spear320 declarations */
......
arch/arm/mach-spear3xx/include/mach/misc_regs.h
View file @ 5df33a62
......@@ -15,150 +15,8 @@
#define __MACH_MISC_REGS_H
#include <mach/hardware.h>
#include <mach/spear.h>
#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
#define SOC_CFG_CTR (MISC_BASE + 0x000)
#define DIAG_CFG_CTR (MISC_BASE + 0x004)
#define PLL1_CTR (MISC_BASE + 0x008)
#define PLL1_FRQ (MISC_BASE + 0x00C)
#define PLL1_MOD (MISC_BASE + 0x010)
#define PLL2_CTR (MISC_BASE + 0x014)
/* PLL_CTR register masks */
#define PLL_ENABLE 2
#define PLL_MODE_SHIFT 4
#define PLL_MODE_MASK 0x3
#define PLL_MODE_NORMAL 0
#define PLL_MODE_FRACTION 1
#define PLL_MODE_DITH_DSB 2
#define PLL_MODE_DITH_SSB 3
#define PLL2_FRQ (MISC_BASE + 0x018)
/* PLL FRQ register masks */
#define PLL_DIV_N_SHIFT 0
#define PLL_DIV_N_MASK 0xFF
#define PLL_DIV_P_SHIFT 8
#define PLL_DIV_P_MASK 0x7
#define PLL_NORM_FDBK_M_SHIFT 24
#define PLL_NORM_FDBK_M_MASK 0xFF
#define PLL_DITH_FDBK_M_SHIFT 16
#define PLL_DITH_FDBK_M_MASK 0xFFFF
#define PLL2_MOD (MISC_BASE + 0x01C)
#define PLL_CLK_CFG (MISC_BASE + 0x020)
#define CORE_CLK_CFG (MISC_BASE + 0x024)
/* CORE CLK CFG register masks */
#define PLL_HCLK_RATIO_SHIFT 10
#define PLL_HCLK_RATIO_MASK 0x3
#define HCLK_PCLK_RATIO_SHIFT 8
#define HCLK_PCLK_RATIO_MASK 0x3
#define PERIP_CLK_CFG (MISC_BASE + 0x028)
/* PERIP_CLK_CFG register masks */
#define UART_CLK_SHIFT 4
#define UART_CLK_MASK 0x1
#define FIRDA_CLK_SHIFT 5
#define FIRDA_CLK_MASK 0x3
#define GPT0_CLK_SHIFT 8
#define GPT1_CLK_SHIFT 11
#define GPT2_CLK_SHIFT 12
#define GPT_CLK_MASK 0x1
#define AUX_CLK_PLL3_VAL 0
#define AUX_CLK_PLL1_VAL 1
#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
/* PERIP1_CLK_ENB register masks */
#define UART_CLK_ENB 3
#define SSP_CLK_ENB 5
#define I2C_CLK_ENB 7
#define JPEG_CLK_ENB 8
#define FIRDA_CLK_ENB 10
#define GPT1_CLK_ENB 11
#define GPT2_CLK_ENB 12
#define ADC_CLK_ENB 15
#define RTC_CLK_ENB 17
#define GPIO_CLK_ENB 18
#define DMA_CLK_ENB 19
#define SMI_CLK_ENB 21
#define GMAC_CLK_ENB 23
#define USBD_CLK_ENB 24
#define USBH_CLK_ENB 25
#define C3_CLK_ENB 31
#define SOC_CORE_ID (MISC_BASE + 0x030)
#define RAS_CLK_ENB (MISC_BASE + 0x034)
#define PERIP1_SOF_RST (MISC_BASE + 0x038)
/* PERIP1_SOF_RST register masks */
#define JPEG_SOF_RST 8
#define SOC_USER_ID (MISC_BASE + 0x03C)
#define RAS_SOF_RST (MISC_BASE + 0x040)
#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
/* gpt synthesizer register masks */
#define GPT_MSCALE_SHIFT 0
#define GPT_MSCALE_MASK 0xFFF
#define GPT_NSCALE_SHIFT 12
#define GPT_NSCALE_MASK 0xF
#define AMEM_CLK_CFG (MISC_BASE + 0x050)
#define EXPI_CLK_CFG (MISC_BASE + 0x054)
#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
#define UART_CLK_SYNT (MISC_BASE + 0x064)
#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
/* aux clk synthesiser register masks for irda to ras4 */
#define AUX_SYNT_ENB 31
#define AUX_EQ_SEL_SHIFT 30
#define AUX_EQ_SEL_MASK 1
#define AUX_EQ1_SEL 0
#define AUX_EQ2_SEL 1
#define AUX_XSCALE_SHIFT 16
#define AUX_XSCALE_MASK 0xFFF
#define AUX_YSCALE_SHIFT 0
#define AUX_YSCALE_MASK 0xFFF
#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
#define ICM2_ARB_CFG (MISC_BASE + 0x080)
#define ICM3_ARB_CFG (MISC_BASE + 0x084)
#define ICM4_ARB_CFG (MISC_BASE + 0x088)
#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
#define ICM6_ARB_CFG (MISC_BASE + 0x090)
#define ICM7_ARB_CFG (MISC_BASE + 0x094)
#define ICM8_ARB_CFG (MISC_BASE + 0x098)
#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
#define BIST4_CFG_CTR (MISC_BASE + 0x100)
#define BIST5_CFG_CTR (MISC_BASE + 0x104)
#define BIST1_STS_RES (MISC_BASE + 0x108)
#define BIST2_STS_RES (MISC_BASE + 0x10C)
#define BIST3_STS_RES (MISC_BASE + 0x110)
#define BIST4_STS_RES (MISC_BASE + 0x114)
#define BIST5_STS_RES (MISC_BASE + 0x118)
#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
#endif /* __MACH_MISC_REGS_H */
arch/arm/mach-spear3xx/include/mach/spear.h
View file @ 5df33a62
......@@ -78,4 +78,17 @@
#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
/* SPEAr320 Macros */
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000)
#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
#define SPEAR320_UARTX_PCLK_MASK 0x1
#define SPEAR320_UART2_PCLK_SHIFT 8
#define SPEAR320_UART3_PCLK_SHIFT 9
#define SPEAR320_UART4_PCLK_SHIFT 10
#define SPEAR320_UART5_PCLK_SHIFT 11
#define SPEAR320_UART6_PCLK_SHIFT 12
#define SPEAR320_RS485_PCLK_SHIFT 13
#endif /* __MACH_SPEAR3XX_H */
arch/arm/mach-spear3xx/spear320.c
View file @ 5df33a62
......@@ -16,6 +16,7 @@
#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/hardware.h>
#include <mach/spear.h>
/* pad multiplexing support */
/* muxing registers */
......
arch/arm/mach-spear3xx/spear3xx.c
View file @ 5df33a62
......@@ -511,6 +511,8 @@ static void __init spear3xx_timer_init(void)
char pclk_name[] = "pll3_48m_clk";
struct clk *gpt_clk, *pclk;
spear3xx_clk_init();
/* get the system timer clock */
gpt_clk = clk_get_sys("gpt0", NULL);
if (IS_ERR(gpt_clk)) {
......
arch/arm/mach-spear6xx/Makefile
View file @ 5df33a62
......@@ -3,4 +3,4 @@
#
# common files
obj-y += clock.o spear6xx.o
obj-y += spear6xx.o
arch/arm/mach-spear6xx/clock.c deleted 100644 → 0
View file @ f8abc080
This diff is collapsed.
arch/arm/mach-spear6xx/include/mach/misc_regs.h
View file @ 5df33a62
......@@ -15,160 +15,8 @@
#define __MACH_MISC_REGS_H
#include <mach/hardware.h>
#include <mach/spear.h>
#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
#define SOC_CFG_CTR (MISC_BASE + 0x000)
#define DIAG_CFG_CTR (MISC_BASE + 0x004)
#define PLL1_CTR (MISC_BASE + 0x008)
#define PLL1_FRQ (MISC_BASE + 0x00C)
#define PLL1_MOD (MISC_BASE + 0x010)
#define PLL2_CTR (MISC_BASE + 0x014)
/* PLL_CTR register masks */
#define PLL_ENABLE 2
#define PLL_MODE_SHIFT 4
#define PLL_MODE_MASK 0x3
#define PLL_MODE_NORMAL 0
#define PLL_MODE_FRACTION 1
#define PLL_MODE_DITH_DSB 2
#define PLL_MODE_DITH_SSB 3
#define PLL2_FRQ (MISC_BASE + 0x018)
/* PLL FRQ register masks */
#define PLL_DIV_N_SHIFT 0
#define PLL_DIV_N_MASK 0xFF
#define PLL_DIV_P_SHIFT 8
#define PLL_DIV_P_MASK 0x7
#define PLL_NORM_FDBK_M_SHIFT 24
#define PLL_NORM_FDBK_M_MASK 0xFF
#define PLL_DITH_FDBK_M_SHIFT 16
#define PLL_DITH_FDBK_M_MASK 0xFFFF
#define PLL2_MOD (MISC_BASE + 0x01C)
#define PLL_CLK_CFG (MISC_BASE + 0x020)
#define CORE_CLK_CFG (MISC_BASE + 0x024)
/* CORE CLK CFG register masks */
#define PLL_HCLK_RATIO_SHIFT 10
#define PLL_HCLK_RATIO_MASK 0x3
#define HCLK_PCLK_RATIO_SHIFT 8
#define HCLK_PCLK_RATIO_MASK 0x3
#define PERIP_CLK_CFG (MISC_BASE + 0x028)
/* PERIP_CLK_CFG register masks */
#define CLCD_CLK_SHIFT 2
#define CLCD_CLK_MASK 0x3
#define UART_CLK_SHIFT 4
#define UART_CLK_MASK 0x1
#define FIRDA_CLK_SHIFT 5
#define FIRDA_CLK_MASK 0x3
#define GPT0_CLK_SHIFT 8
#define GPT1_CLK_SHIFT 10
#define GPT2_CLK_SHIFT 11
#define GPT3_CLK_SHIFT 12
#define GPT_CLK_MASK 0x1
#define AUX_CLK_PLL3_VAL 0
#define AUX_CLK_PLL1_VAL 1
#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
/* PERIP1_CLK_ENB register masks */
#define UART0_CLK_ENB 3
#define UART1_CLK_ENB 4
#define SSP0_CLK_ENB 5
#define SSP1_CLK_ENB 6
#define I2C_CLK_ENB 7
#define JPEG_CLK_ENB 8
#define FSMC_CLK_ENB 9
#define FIRDA_CLK_ENB 10
#define GPT2_CLK_ENB 11
#define GPT3_CLK_ENB 12
#define GPIO2_CLK_ENB 13
#define SSP2_CLK_ENB 14
#define ADC_CLK_ENB 15
#define GPT1_CLK_ENB 11
#define RTC_CLK_ENB 17
#define GPIO1_CLK_ENB 18
#define DMA_CLK_ENB 19
#define SMI_CLK_ENB 21
#define CLCD_CLK_ENB 22
#define GMAC_CLK_ENB 23
#define USBD_CLK_ENB 24
#define USBH0_CLK_ENB 25
#define USBH1_CLK_ENB 26
#define SOC_CORE_ID (MISC_BASE + 0x030)
#define RAS_CLK_ENB (MISC_BASE + 0x034)
#define PERIP1_SOF_RST (MISC_BASE + 0x038)
/* PERIP1_SOF_RST register masks */
#define JPEG_SOF_RST 8
#define SOC_USER_ID (MISC_BASE + 0x03C)
#define RAS_SOF_RST (MISC_BASE + 0x040)
#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
/* gpt synthesizer register masks */
#define GPT_MSCALE_SHIFT 0
#define GPT_MSCALE_MASK 0xFFF
#define GPT_NSCALE_SHIFT 12
#define GPT_NSCALE_MASK 0xF
#define AMEM_CLK_CFG (MISC_BASE + 0x050)
#define EXPI_CLK_CFG (MISC_BASE + 0x054)
#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
#define UART_CLK_SYNT (MISC_BASE + 0x064)
#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
/* aux clk synthesiser register masks for irda to ras4 */
#define AUX_SYNT_ENB 31
#define AUX_EQ_SEL_SHIFT 30
#define AUX_EQ_SEL_MASK 1
#define AUX_EQ1_SEL 0
#define AUX_EQ2_SEL 1
#define AUX_XSCALE_SHIFT 16
#define AUX_XSCALE_MASK 0xFFF
#define AUX_YSCALE_SHIFT 0
#define AUX_YSCALE_MASK 0xFFF
#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
#define ICM2_ARB_CFG (MISC_BASE + 0x080)
#define ICM3_ARB_CFG (MISC_BASE + 0x084)
#define ICM4_ARB_CFG (MISC_BASE + 0x088)
#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
#define ICM6_ARB_CFG (MISC_BASE + 0x090)
#define ICM7_ARB_CFG (MISC_BASE + 0x094)
#define ICM8_ARB_CFG (MISC_BASE + 0x098)
#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
#define BIST4_CFG_CTR (MISC_BASE + 0x100)
#define BIST5_CFG_CTR (MISC_BASE + 0x104)
#define BIST1_STS_RES (MISC_BASE + 0x108)
#define BIST2_STS_RES (MISC_BASE + 0x10C)
#define BIST3_STS_RES (MISC_BASE + 0x110)
#define BIST4_STS_RES (MISC_BASE + 0x114)
#define BIST5_STS_RES (MISC_BASE + 0x118)
#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
#endif /* __MACH_MISC_REGS_H */
arch/arm/mach-spear6xx/spear6xx.c
View file @ 5df33a62
......@@ -56,9 +56,6 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
void __init spear6xx_map_io(void)
{
iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
/* This will initialize clock framework */
spear6xx_clk_init();
}
static void __init spear6xx_timer_init(void)
......@@ -66,6 +63,8 @@ static void __init spear6xx_timer_init(void)
char pclk_name[] = "pll3_48m_clk";
struct clk *gpt_clk, *pclk;
spear6xx_clk_init();
/* get the system timer clock */
gpt_clk = clk_get_sys("gpt0", NULL);
if (IS_ERR(gpt_clk)) {
......
arch/arm/plat-spear/Makefile
View file @ 5df33a62
......@@ -3,6 +3,6 @@
#
# Common support
obj-y := clock.o restart.o time.o
obj-y := restart.o time.o
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
arch/arm/plat-spear/clock.c deleted 100644 → 0
View file @ f8abc080
This diff is collapsed.
arch/arm/plat-spear/include/plat/clock.h deleted 100644 → 0
View file @ f8abc080
/*
* arch/arm/plat-spear/include/plat/clock.h
*
* Clock framework definitions for SPEAr platform
*
* Copyright (C) 2009 ST Microelectronics
* Viresh Kumar<viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __PLAT_CLOCK_H
#define __PLAT_CLOCK_H
#include <linux/list.h>
#include <linux/clkdev.h>
#include <linux/types.h>
/* clk structure flags */
#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
#define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */
/**
* struct clkops - clock operations
* @enable: pointer to clock enable function
* @disable: pointer to clock disable function
*/
struct clkops {
int (*enable) (struct clk *);
void (*disable) (struct clk *);
};
/**
* struct pclk_info - parents info
* @pclk: pointer to parent clk
* @pclk_val: value to be written for selecting this parent
*/
struct pclk_info {
struct clk *pclk;
u8 pclk_val;
};
/**
* struct pclk_sel - parents selection configuration
* @pclk_info: pointer to array of parent clock info
* @pclk_count: number of parents
* @pclk_sel_reg: register for selecting a parent
* @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
*/
struct pclk_sel {
struct pclk_info *pclk_info;
u8 pclk_count;
void __iomem *pclk_sel_reg;
unsigned int pclk_sel_mask;
};
/**
* struct rate_config - clk rate configurations
* @tbls: array of device specific clk rate tables, in ascending order of rates
* @count: size of tbls array
* @default_index: default setting when originally disabled
*/
struct rate_config {
void *tbls;
u8 count;
u8 default_index;
};
/**
* struct clk - clock structure
* @usage_count: num of users who enabled this clock
* @flags: flags for clock properties
* @rate: programmed clock rate in Hz
* @en_reg: clk enable/disable reg
* @en_reg_bit: clk enable/disable bit
* @ops: clk enable/disable ops - generic_clkops selected if NULL
* @recalc: pointer to clock rate recalculate function
* @set_rate: pointer to clock set rate function
* @calc_rate: pointer to clock get rate function for index
* @rate_config: rate configuration information, used by set_rate
* @div_factor: division factor to parent clock.
* @pclk: current parent clk
* @pclk_sel: pointer to parent selection structure
* @pclk_sel_shift: register shift for selecting parent of this clock
* @children: list for childrens or this clock
* @sibling: node for list of clocks having same parents
* @private_data: clock specific private data
* @node: list to maintain clocks linearly
* @cl: clocklook up associated with this clock
* @dent: object for debugfs
*/
struct clk {
unsigned int usage_count;
unsigned int flags;
unsigned long rate;
void __iomem *en_reg;
u8 en_reg_bit;
const struct clkops *ops;
int (*recalc) (struct clk *);
int (*set_rate) (struct clk *, unsigned long rate);
unsigned long (*calc_rate)(struct clk *, int index);
struct rate_config rate_config;
unsigned int div_factor;
struct clk *pclk;
struct pclk_sel *pclk_sel;
unsigned int pclk_sel_shift;
struct list_head children;
struct list_head sibling;
void *private_data;
#ifdef CONFIG_DEBUG_FS
struct list_head node;
struct clk_lookup *cl;
struct dentry *dent;
#endif
};
/* pll configuration structure */
struct pll_clk_masks {
u32 mode_mask;
u32 mode_shift;
u32 norm_fdbk_m_mask;
u32 norm_fdbk_m_shift;
u32 dith_fdbk_m_mask;
u32 dith_fdbk_m_shift;
u32 div_p_mask;
u32 div_p_shift;
u32 div_n_mask;
u32 div_n_shift;
};
struct pll_clk_config {
void __iomem *mode_reg;
void __iomem *cfg_reg;
struct pll_clk_masks *masks;
};
/* pll clk rate config structure */
struct pll_rate_tbl {
u8 mode;
u16 m;
u8 n;
u8 p;
};
/* ahb and apb bus configuration structure */
struct bus_clk_masks {
u32 mask;
u32 shift;
};
struct bus_clk_config {
void __iomem *reg;
struct bus_clk_masks *masks;
};
/* ahb and apb clk bus rate config structure */
struct bus_rate_tbl {
u8 div;
};
/* Aux clk configuration structure: applicable to UART and FIRDA */
struct aux_clk_masks {
u32 eq_sel_mask;
u32 eq_sel_shift;
u32 eq1_mask;
u32 eq2_mask;
u32 xscale_sel_mask;
u32 xscale_sel_shift;
u32 yscale_sel_mask;
u32 yscale_sel_shift;
};
struct aux_clk_config {
void __iomem *synth_reg;
struct aux_clk_masks *masks;
};
/* aux clk rate config structure */
struct aux_rate_tbl {
u16 xscale;
u16 yscale;
u8 eq;
};
/* GPT clk configuration structure */
struct gpt_clk_masks {
u32 mscale_sel_mask;
u32 mscale_sel_shift;
u32 nscale_sel_mask;
u32 nscale_sel_shift;
};
struct gpt_clk_config {
void __iomem *synth_reg;
struct gpt_clk_masks *masks;
};
/* gpt clk rate config structure */
struct gpt_rate_tbl {
u16 mscale;
u16 nscale;
};
/* clcd clk configuration structure */
struct clcd_synth_masks {
u32 div_factor_mask;
u32 div_factor_shift;
};
struct clcd_clk_config {
void __iomem *synth_reg;
struct clcd_synth_masks *masks;
};
/* clcd clk rate config structure */
struct clcd_rate_tbl {
u16 div;
};
/* platform specific clock functions */
void __init clk_init(void);
void clk_register(struct clk_lookup *cl);
void recalc_root_clocks(void);
/* clock recalc & set rate functions */
int follow_parent(struct clk *clk);
unsigned long pll_calc_rate(struct clk *clk, int index);
int pll_clk_recalc(struct clk *clk);
int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long bus_calc_rate(struct clk *clk, int index);
int bus_clk_recalc(struct clk *clk);
int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long gpt_calc_rate(struct clk *clk, int index);
int gpt_clk_recalc(struct clk *clk);
int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long aux_calc_rate(struct clk *clk, int index);
int aux_clk_recalc(struct clk *clk);
int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long clcd_calc_rate(struct clk *clk, int index);
int clcd_clk_recalc(struct clk *clk);
int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
#endif /* __PLAT_CLOCK_H */
drivers/clk/spear/Makefile
View file @ 5df33a62
......@@ -3,3 +3,6 @@
#
obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx_clock.o
obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx_clock.o
drivers/clk/spear/spear3xx_clock.c 0 → 100644
View file @ 5df33a62
This diff is collapsed.
drivers/clk/spear/spear6xx_clock.c 0 → 100644
View file @ 5df33a62
This diff is collapsed.
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