Import 2.1.92pre2

arch/alpha/Makefile

@@ -10,8 +10,40 @@
 
 NM := nm -B
 
+#LINKFLAGS = -static -T arch/alpha/vmlinux.lds
+#CFLAGS := $(CFLAGS) -pipe -mno-fp-regs -ffixed-8
+
+ifdef CONFIG_CROSSCOMPILE
+# enable this for linking under OSF/1:
+LINKFLAGS = -non_shared -T 0xfffffc0000310000 -N
+else
+ elf=$(shell if $(LD) --help | grep elf64alpha >/dev/null; then echo yes; fi)
+ ifeq ($(elf),yes)
+#   LINKFLAGS = -static -Ttext 0xfffffc0000310000 -N
 LINKFLAGS = -static -T arch/alpha/vmlinux.lds
-CFLAGS := $(CFLAGS) -pipe -mno-fp-regs -ffixed-8
+ else
+   LINKFLAGS = -static -T arch/alpha/vmlinux.lds -N
+ endif
+# GNU gcc/cc1/as can use pipes instead of temporary files
+CFLAGS := $(CFLAGS) -pipe
+endif
+
+CFLAGS := $(CFLAGS) -mno-fp-regs -ffixed-8 -Wno-uninitialized
+
+# determine if we can use the BWX instructions with GAS
+$(shell rm -f ./GAS_VER)
+$(shell $(AS) --version >& ./GAS_VER)
+OLD_GAS := $(shell if cat ./GAS_VER | grep 'version 2.7' > /dev/null; then echo yes; else echo no; fi)
+$(shell rm -f ./GAS_VER)
+
+ifneq ($(OLD_GAS),yes)
+ CFLAGS := $(CFLAGS) -Wa,-m21164a -DBWX_USABLE
+
+# if PYXIS, then enable use of BWIO space
+ ifeq ($(CONFIG_ALPHA_PYXIS),y)
+  CFLAGS := $(CFLAGS) -DBWIO_ENABLED
+ endif
+endif
 
 HEAD := arch/alpha/kernel/head.o
 
@@ -23,7 +55,7 @@ ifeq ($(CONFIG_MATHEMU),y)
   CORE_FILES := $(CORE_FILES) arch/alpha/math-emu/math-emu.o
 endif
 
-LIBS := arch/alpha/lib/lib.a $(LIBS) arch/alpha/lib/lib.a
+LIBS := $(TOPDIR)/arch/alpha/lib/lib.a $(LIBS) $(TOPDIR)/arch/alpha/lib/lib.a
 
 MAKEBOOT = $(MAKE) -C arch/$(ARCH)/boot
 

arch/alpha/boot/bootp.c

@@ -11,11 +11,13 @@
 #include <linux/string.h>
 #include <linux/version.h>
 #include <linux/mm.h>
+#include <linux/config.h>
 
 #include <asm/system.h>
 #include <asm/console.h>
 #include <asm/hwrpb.h>
 #include <asm/pgtable.h>
+#include <asm/io.h>
 
 #include <stdarg.h>
 
@@ -156,7 +158,8 @@ void pal_init(void)
 	printk("Ok (rev %lx)\n", rev);
 	/* remove the old virtual page-table mapping */
 	L1[1] = 0;
-	flush_tlb_all();
+
+	tbia(); /* do it directly in case we are SMP */
 }
 
 static inline long load(unsigned long dst,
@@ -189,30 +192,59 @@ extern char _end;
 
 void start_kernel(void)
 {
-	long i;
-	int nbytes;
-	char envval[256];
+	static long i;
+	static int nbytes;
+	/*
+	 * note that this crufty stuff with static and envval and envbuf
+	 * is because:
+	 *
+	 * 1. frequently, the stack is is short, and we don't want to overrun;
+	 * 2. frequently the stack is where we are going to copy the kernel to;
+	 * 3. a certain SRM console required the GET_ENV output to stack.
+	 */
+	static char envval[256];
+	char envbuf[256];
 
 	printk("Linux/AXP bootp loader for Linux " UTS_RELEASE "\n");
 	if (hwrpb.pagesize != 8192) {
-		printk("Expected 8kB pages, got %ldkB\n", hwrpb.pagesize >> 10);
+		printk("Expected 8kB pages, got %ldkB\n",
+		       hwrpb.pagesize >> 10);
 		return;
 	}
 	pal_init();
 
 	nbytes = dispatch(CCB_GET_ENV, ENV_BOOTED_OSFLAGS,
-			  envval, sizeof(envval));
-	if (nbytes < 0) {
+			  envbuf, sizeof(envbuf));
+	if (nbytes < 0 || nbytes >= sizeof(envbuf)) {
 		nbytes = 0;
 	}
-	envval[nbytes] = '\0';
-	strcpy((char*)ZERO_PAGE, envval);
-
-	printk("Loading the kernel ...\n");
+	envbuf[nbytes] = '\0';
+	memcpy(envval, envbuf, nbytes+1);
+	printk("Loading the kernel...'%s'\n", envval);
 
 	/* NOTE: *no* callbacks or printouts from here on out!!! */
 
+#if 1
+	/*
+	 * this is a hack, as some consoles seem to get virtual 20000000
+	 * (ie where the SRM console puts the kernel bootp image) memory
+	 * overlapping physical 310000 memory, which causes real problems
+	 * when attempting to copy the former to the latter... :-(
+	 *
+	 * so, we first move the kernel virtual-to-physical way above where
+	 * we physically want the kernel to end up, then copy it from there
+	 * to its final resting place... ;-}
+	 *
+	 * sigh...
+	 */
+
+        i = load(START_ADDR+(4*KERNEL_SIZE), KERNEL_ORIGIN, KERNEL_SIZE);
+        i = load(START_ADDR, START_ADDR+(4*KERNEL_SIZE), KERNEL_SIZE);
+#else
 	i = load(START_ADDR, KERNEL_ORIGIN, KERNEL_SIZE);
+#endif
+
+	strcpy((char*)ZERO_PAGE, envval);
 
 	runkernel();
 

arch/alpha/config.in

@@ -6,11 +6,13 @@ mainmenu_name "Kernel configuration of Linux for Alpha machines"
 
 # clear all implied options (don't want default values for those):
 unset CONFIG_CROSSCOMPILE CONFIG_NATIVE
-unset CONFIG_ALPHA_EV4 CONFIG_ALPHA_EV5
+unset CONFIG_ALPHA_EV4 CONFIG_ALPHA_EV5 CONFIG_ALPHA_EV6
 unset CONFIG_PCI CONFIG_ALPHA_EISA
 unset CONFIG_ALPHA_LCA CONFIG_ALPHA_APECS CONFIG_ALPHA_CIA
 unset CONFIG_ALPHA_T2 CONFIG_ALPHA_PYXIS
+unset CONFIG_ALPHA_TSUNAMI CONFIG_ALPHA_MCPCIA
 unset CONFIG_ALPHA_NEED_ROUNDING_EMULATION
+unset CONFIG_ALPHA_SRM CONFIG_ALPHA_SRM_SETUP
 
 mainmenu_option next_comment
 comment 'Code maturity level options'
@@ -48,13 +50,16 @@ choice 'Alpha system type' \
 	 PC164		CONFIG_ALPHA_PC164		\
 	 LX164		CONFIG_ALPHA_LX164		\
 	 SX164		CONFIG_ALPHA_SX164		\
+	 DP264		CONFIG_ALPHA_DP264		\
 	 Jensen		CONFIG_ALPHA_JENSEN		\
 	 Noname		CONFIG_ALPHA_NONAME		\
+	 Takara		CONFIG_ALPHA_TAKARA		\
 	 Mikasa		CONFIG_ALPHA_MIKASA		\
 	 Noritake	CONFIG_ALPHA_NORITAKE		\
 	 Alcor		CONFIG_ALPHA_ALCOR		\
 	 Miata		CONFIG_ALPHA_MIATA		\
 	 Sable		CONFIG_ALPHA_SABLE		\
+	 Rawhide	CONFIG_ALPHA_RAWHIDE		\
 	 AlphaBook1	CONFIG_ALPHA_BOOK1		\
 	 Ruffian	CONFIG_ALPHA_RUFFIAN		\
 	 Platform2000	CONFIG_ALPHA_P2K" Cabriolet
@@ -78,7 +83,8 @@ then
 	define_bool CONFIG_ALPHA_APECS y
 fi
 if [ "$CONFIG_ALPHA_EB164" = "y" -o "$CONFIG_ALPHA_PC164" = "y" \
-	-o "$CONFIG_ALPHA_ALCOR" = "y" -o "$CONFIG_ALPHA_XLT" = "y" ]
+	-o "$CONFIG_ALPHA_ALCOR" = "y" -o "$CONFIG_ALPHA_XLT" = "y" \
+	-o "$CONFIG_ALPHA_TAKARA" = "y" ]
 then
 	define_bool CONFIG_PCI y
 	define_bool CONFIG_ALPHA_EV5 y
@@ -86,9 +92,7 @@ then
 fi
 if [ "$CONFIG_ALPHA_MIKASA" = "y" -o "$CONFIG_ALPHA_NORITAKE" = "y" ]
 then
-	choice 'CPU daughtercard' \
-		"Pinnacle	CONFIG_ALPHA_PINNACLE \
-		Primo		CONFIG_ALPHA_PRIMO" Primo
+	bool 'EV5 CPU daughtercard (model 5/xxx)?' CONFIG_ALPHA_PRIMO
 	if [ "$CONFIG_ALPHA_PRIMO" = "y" ]
 	then
 		define_bool CONFIG_ALPHA_EV5 y
@@ -102,7 +106,13 @@ fi
 if [ "$CONFIG_ALPHA_SABLE" = "y" ]
 then
 	define_bool CONFIG_PCI y
+	bool 'EV5 CPU(s) (model 5/xxx)?' CONFIG_ALPHA_GAMMA
+	if [ "$CONFIG_ALPHA_GAMMA" = "y" ]
+	then
+		define_bool CONFIG_ALPHA_EV5 y
+	else
 	define_bool CONFIG_ALPHA_EV4 y
+	fi
 	define_bool CONFIG_ALPHA_T2 y
 fi
 if [ "$CONFIG_ALPHA_MIATA" = "y" -o "$CONFIG_ALPHA_LX164" = "y" \
@@ -112,6 +122,18 @@ then
 	define_bool CONFIG_ALPHA_EV5 y
 	define_bool CONFIG_ALPHA_PYXIS y
 fi
+if [ "$CONFIG_ALPHA_DP264" = "y" ]
+then
+	define_bool CONFIG_PCI y
+	define_bool CONFIG_ALPHA_EV6 y
+	define_bool CONFIG_ALPHA_TSUNAMI y
+fi
+if [ "$CONFIG_ALPHA_RAWHIDE" = "y" ]
+then
+	define_bool CONFIG_PCI y
+	define_bool CONFIG_ALPHA_EV5 y
+	define_bool CONFIG_ALPHA_MCPCIA y
+fi
 if [ "$CONFIG_ALPHA_JENSEN" = "y" ]
 then
 	define_bool CONFIG_ALPHA_EV4 y
@@ -127,12 +149,19 @@ if [ "$CONFIG_ALPHA_CABRIOLET" = "y" -o "$CONFIG_ALPHA_AVANTI" = "y" \
 	-o "$CONFIG_ALPHA_MIKASA" = "y" -o "$CONFIG_ALPHA_ALCOR" = "y" \
 	-o "$CONFIG_ALPHA_SABLE" = "y" -o "$CONFIG_ALPHA_MIATA" = "y" \
 	-o "$CONFIG_ALPHA_NORITAKE" = "y" -o "$CONFIG_ALPHA_PC164" = "y" \
-	-o "$CONFIG_ALPHA_LX164" = "y" -o "$CONFIG_ALPHA_SX164" = "y" ]
+	-o "$CONFIG_ALPHA_LX164" = "y" -o "$CONFIG_ALPHA_SX164" = "y" \
+	-o "$CONFIG_ALPHA_DP264" = "y" -o "$CONFIG_ALPHA_RAWHIDE" = "y" ]
 then
-	bool 'Using SRM as bootloader' CONFIG_ALPHA_SRM
+  bool 'Use SRM as bootloader' CONFIG_ALPHA_SRM
+  if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
+    if [ "$CONFIG_ALPHA_SRM" = "y" ]; then
+      bool '  Use SRM PCI setup' CONFIG_ALPHA_SRM_SETUP
+    fi
+  fi
 fi
 if [ "$CONFIG_ALPHA_ALCOR" = "y" -o "$CONFIG_ALPHA_MIKASA" = "y" \
-	-o "$CONFIG_ALPHA_SABLE" = "y" -o "$CONFIG_ALPHA_NORITAKE" = "y" ]
+	-o "$CONFIG_ALPHA_SABLE" = "y" -o "$CONFIG_ALPHA_NORITAKE" = "y" \
+	-o "$CONFIG_ALPHA_RAWHIDE" = "y" ]
 then
 	define_bool CONFIG_ALPHA_EISA y
 fi
@@ -141,8 +170,13 @@ then
 	define_bool CONFIG_ALPHA_AVANTI y
 fi
 
+#bool 'Echo console messages on /dev/ttyS0 (COM1)' CONFIG_SERIAL_ECHO
+
 if [ "$CONFIG_PCI" = "y" ]; then
   bool 'TGA Console Support' CONFIG_TGA_CONSOLE
+#  if [ "$CONFIG_TGA_CONSOLE" = "y" ]; then
+#    bool 'VGA Console Support' CONFIG_VGA_CONSOLE
+#  fi
   if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
     bool 'PCI bridge optimization (experimental)' CONFIG_PCI_OPTIMIZE
   fi
@@ -216,17 +250,6 @@ if [ "$CONFIG_CD_NO_IDESCSI" != "n" ]; then
 fi
 endmenu
 
-# Conditionally compile in the Uniform CD-ROM driver
-if [ "$CONFIG_BLK_DEV_IDECD" = "y" -o "$CONFIG_BLK_DEV_SR" = "y" -o "$CONFIG_SBPCD" = "y" -o "$CONFIG_MCD" = "y" -o "$CONFIG_CM206" = "y" -o "$CONFIG_CDU31A" = "y" ]; then
-  define_bool CONFIG_CDROM y
-else
-  if [ "$CONFIG_BLK_DEV_IDECD" = "m" -o "$CONFIG_BLK_DEV_SR" = "m" -o "$CONFIG_SBPCD" = "m" -o "$CONFIG_MCD" = "m" -o "$CONFIG_CM206" = "m" -o "$CONFIG_CDU31A" = "m" ]; then
-    define_bool CONFIG_CDROM m
-  else
-    define_bool CONFIG_CDROM n
-  fi
-fi
-
 source fs/Config.in
 
 source fs/nls/Config.in

arch/alpha/defconfig

@@ -27,14 +27,20 @@ CONFIG_NATIVE=y
 # CONFIG_ALPHA_EB64P is not set
 # CONFIG_ALPHA_EB164 is not set
 # CONFIG_ALPHA_PC164 is not set
+# CONFIG_ALPHA_LX164 is not set
+# CONFIG_ALPHA_SX164 is not set
+# CONFIG_ALPHA_DP264 is not set
 # CONFIG_ALPHA_JENSEN is not set
 # CONFIG_ALPHA_NONAME is not set
+# CONFIG_ALPHA_TAKARA is not set
 # CONFIG_ALPHA_MIKASA is not set
 # CONFIG_ALPHA_NORITAKE is not set
 CONFIG_ALPHA_ALCOR=y
 # CONFIG_ALPHA_MIATA is not set
 # CONFIG_ALPHA_SABLE is not set
+# CONFIG_ALPHA_RAWHIDE is not set
 # CONFIG_ALPHA_BOOK1 is not set
+# CONFIG_ALPHA_RUFFIAN is not set
 # CONFIG_ALPHA_P2K is not set
 CONFIG_PCI=y
 CONFIG_ALPHA_EV5=y
@@ -214,7 +220,6 @@ CONFIG_DE4X5=y
 # CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
 #
 # CONFIG_CD_NO_IDESCSI is not set
-CONFIG_CDROM=y
 
 #
 # Filesystems

arch/alpha/kernel/Makefile

@@ -8,9 +8,9 @@
 # Note 2! The CFLAGS definitions are now in the main makefile...
 
 .S.s:
-	$(CPP) -D__ASSEMBLY__ -traditional $< -o $*.s
+	$(CPP) -D__ASSEMBLY__ $(AFLAGS) -traditional    $< -o $*.s
 .S.o:
-	$(CC) -D__ASSEMBLY__ -traditional -c $< -o $*.o
+	$(CC)  -D__ASSEMBLY__ $(AFLAGS) -traditional -c $< -o $*.o
 
 all: kernel.o head.o
 
@@ -35,19 +35,29 @@ endif
 ifdef CONFIG_ALPHA_T2
 O_OBJS   += t2.o
 endif
+ifdef CONFIG_ALPHA_TSUNAMI
+O_OBJS   += tsunami.o
+endif
+ifdef CONFIG_ALPHA_MCPCIA
+O_OBJS   += mcpcia.o
+endif
+
 ifneq ($(CONFIG_ALPHA_PC164)$(CONFIG_ALPHA_LX164),nn)
 O_OBJS   += smc37c93x.o
 endif
-ifdef CONFIG_ALPHA_SX164
+ifneq ($(CONFIG_ALPHA_SX164)$(CONFIG_ALPHA_MIATA)$(CONFIG_ALPHA_DP264),nnn)
 O_OBJS   += smc37c669.o
 endif
 
+ifdef SMP
+O_OBJS   += smp.o
+endif
 
 all: kernel.o head.o
 
 head.o: head.s
 
 head.s: head.S $(TOPDIR)/include/asm-alpha/system.h
-	$(CPP) -traditional -o $*.s $<
+	$(CPP) -traditional $(AFLAGS) -o $*.s $<
 
 include $(TOPDIR)/Rules.make

arch/alpha/kernel/apecs.c

@@ -18,13 +18,14 @@
 #include <asm/hwrpb.h>
 #include <asm/ptrace.h>
 
-/* NOTE: Herein are back-to-back mb insns.  They are magic. 
-   A plausible explanation is that the i/o controler does not properly
-   handle the system transaction.  Another involves timing.  Ho hum.  */
+/*
+ * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
+ * One plausible explanation is that the i/o controller does not properly
+ * handle the system transaction.  Another involves timing.  Ho hum.
+ */
 
 extern struct hwrpb_struct *hwrpb;
 extern asmlinkage void wrmces(unsigned long mces);
-extern int alpha_sys_type;
 
 /*
  * BIOS32-style PCI interface:
@@ -36,13 +37,16 @@ extern int alpha_sys_type;
 # define DBG(args)
 #endif
 
-#define vulp	volatile unsigned long *
 #define vuip	volatile unsigned int  *
 
 static volatile unsigned int apecs_mcheck_expected = 0;
 static volatile unsigned int apecs_mcheck_taken = 0;
-static unsigned long apecs_jd, apecs_jd1, apecs_jd2;
+static unsigned int apecs_jd, apecs_jd1, apecs_jd2;
 
+#ifdef CONFIG_ALPHA_SRM_SETUP
+unsigned int APECS_DMA_WIN_BASE = APECS_DMA_WIN_BASE_DEFAULT;
+unsigned int APECS_DMA_WIN_SIZE = APECS_DMA_WIN_SIZE_DEFAULT;
+#endif /* SRM_SETUP */
 
 /*
  * Given a bus, device, and function number, compute resulting
@@ -194,7 +198,7 @@ static unsigned int conf_read(unsigned long addr, unsigned char type1)
 		}
 
 		/* reset error status: */
-		*(vulp)APECS_IOC_DCSR = stat0;
+		*(vuip)APECS_IOC_DCSR = stat0;
 		mb();
 		wrmces(0x7);			/* reset machine check */
 		value = 0xffffffff;
@@ -269,7 +273,7 @@ static void conf_write(unsigned long addr, unsigned int value, unsigned char typ
 		}
 
 		/* reset error status: */
-		*(vulp)APECS_IOC_DCSR = stat0;
+		*(vuip)APECS_IOC_DCSR = stat0;
 		mb();
 		wrmces(0x7);			/* reset machine check */
 	}
@@ -424,6 +428,38 @@ unsigned long apecs_init(unsigned long mem_start, unsigned long mem_end)
 	*(vuip)APECS_IOC_TB2R = 0;
 
 #else  /* CONFIG_ALPHA_XL */
+#ifdef CONFIG_ALPHA_SRM_SETUP
+	/* check window 1 for enabled and mapped to 0 */
+	if ((*(vuip)APECS_IOC_PB1R & (1U<<19)) && (*(vuip)APECS_IOC_TB1R == 0))
+	{
+	  APECS_DMA_WIN_BASE = *(vuip)APECS_IOC_PB1R & 0xfff00000U;
+	  APECS_DMA_WIN_SIZE = *(vuip)APECS_IOC_PM1R & 0xfff00000U;
+	  APECS_DMA_WIN_SIZE += 0x00100000U;
+#if 0
+	  printk("apecs_init: using Window 1 settings\n");
+	  printk("apecs_init: PB1R 0x%x PM1R 0x%x TB1R 0x%x\n",
+     		 *(vuip)APECS_IOC_PB1R,
+		 *(vuip)APECS_IOC_PM1R,
+		 *(vuip)APECS_IOC_TB1R);
+#endif
+     	}
+	else	/* check window 2 for enabled and mapped to 0 */
+	if ((*(vuip)APECS_IOC_PB2R & (1U<<19)) && (*(vuip)APECS_IOC_TB2R == 0))
+	{
+	  APECS_DMA_WIN_BASE = *(vuip)APECS_IOC_PB2R & 0xfff00000U;
+	  APECS_DMA_WIN_SIZE = *(vuip)APECS_IOC_PM2R & 0xfff00000U;
+	  APECS_DMA_WIN_SIZE += 0x00100000U;
+#if 0
+     	  printk("apecs_init: using Window 2 settings\n");
+	  printk("apecs_init: PB2R 0x%x PM2R 0x%x TB2R 0x%x\n",
+		 *(vuip)APECS_IOC_PB2R,
+		 *(vuip)APECS_IOC_PM2R,
+		 *(vuip)APECS_IOC_TB2R);
+#endif
+     	}
+	else /* we must use our defaults... */
+#endif /* SRM_SETUP */
+	{
 	/*
 	 * Set up the PCI->physical memory translation windows.
 	 * For now, window 2 is disabled.  In the future, we may
@@ -435,9 +471,11 @@ unsigned long apecs_init(unsigned long mem_start, unsigned long mem_end)
 	*(vuip)APECS_IOC_PB1R  = 1U<<19 | (APECS_DMA_WIN_BASE & 0xfff00000U);
 	*(vuip)APECS_IOC_PM1R  = (APECS_DMA_WIN_SIZE - 1) & 0xfff00000U;
 	*(vuip)APECS_IOC_TB1R  = 0;
+	}
 #endif /* CONFIG_ALPHA_XL */
 
 #ifdef CONFIG_ALPHA_CABRIOLET
+#ifdef NO_LONGER_NEEDED_I_HOPE
 	/*
 	 * JAE: HACK!!! for now, hardwire if configured...
 	 * davidm: Older miniloader versions don't set the clock frequency
@@ -461,6 +499,7 @@ unsigned long apecs_init(unsigned long mem_start, unsigned long mem_end)
 	      sum += *l;
 	    hwrpb->chksum = sum;
 	}
+#endif /* NO_LONGER_NEEDED_I_HOPE */
 #endif /* CONFIG_ALPHA_CABRIOLET */
 
        /*
@@ -483,15 +522,15 @@ unsigned long apecs_init(unsigned long mem_start, unsigned long mem_end)
 
 int apecs_pci_clr_err(void)
 {
-	apecs_jd = *(vulp)APECS_IOC_DCSR;
+	apecs_jd = *(vuip)APECS_IOC_DCSR;
 	if (apecs_jd & 0xffe0L) {
-		apecs_jd1 = *(vulp)APECS_IOC_SEAR;
-		*(vulp)APECS_IOC_DCSR = apecs_jd | 0xffe1L;
-		apecs_jd = *(vulp)APECS_IOC_DCSR;
+		apecs_jd1 = *(vuip)APECS_IOC_SEAR;
+		*(vuip)APECS_IOC_DCSR = apecs_jd | 0xffe1L;
+		apecs_jd = *(vuip)APECS_IOC_DCSR;
 		mb();
 	}
-	*(vulp)APECS_IOC_TBIA = APECS_IOC_TBIA;
-	apecs_jd2 = *(vulp)APECS_IOC_TBIA;
+	*(vuip)APECS_IOC_TBIA = (unsigned int)APECS_IOC_TBIA;
+	apecs_jd2 = *(vuip)APECS_IOC_TBIA;
 	mb();
 	return 0;
 }

arch/alpha/kernel/cia.c

@@ -6,6 +6,7 @@
  *
  */
 #include <linux/kernel.h>
+#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/bios32.h>
 #include <linux/pci.h>
@@ -17,13 +18,14 @@
 #include <asm/ptrace.h>
 #include <asm/mmu_context.h>
 
-/* NOTE: Herein are back-to-back mb insns.  They are magic.
-   A plausible explanation is that the i/o controler does not properly
-   handle the system transaction.  Another involves timing.  Ho hum.  */
+/*
+ * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
+ * One plausible explanation is that the i/o controller does not properly
+ * handle the system transaction.  Another involves timing.  Ho hum.
+ */
 
 extern struct hwrpb_struct *hwrpb;
 extern asmlinkage void wrmces(unsigned long mces);
-extern int alpha_sys_type;
 
 /*
  * Machine check reasons.  Defined according to PALcode sources
@@ -56,13 +58,17 @@ extern int alpha_sys_type;
 # define DBGC(args)
 #endif
 
-#define vulp	volatile unsigned long *
 #define vuip	volatile unsigned int  *
 
 static volatile unsigned int CIA_mcheck_expected = 0;
 static volatile unsigned int CIA_mcheck_taken = 0;
 static unsigned int CIA_jd;
 
+#ifdef CONFIG_ALPHA_SRM_SETUP
+unsigned int CIA_DMA_WIN_BASE = CIA_DMA_WIN_BASE_DEFAULT;
+unsigned int CIA_DMA_WIN_SIZE = CIA_DMA_WIN_SIZE_DEFAULT;
+unsigned long cia_sm_base_r1, cia_sm_base_r2, cia_sm_base_r3;
+#endif /* SRM_SETUP */
 
 /*
  * Given a bus, device, and function number, compute resulting
@@ -271,7 +277,7 @@ static void conf_write(unsigned long addr, unsigned int value,
 		}
 
 		/* reset error status: */
-		*(vulp)CIA_IOC_CIA_ERR = stat0;
+		*(vuip)CIA_IOC_CIA_ERR = stat0;
 		mb();
 		wrmces(0x7);			/* reset machine check */
 		value = 0xffffffff;
@@ -442,6 +448,18 @@ unsigned long cia_init(unsigned long mem_start, unsigned long mem_end)
 		printk("CIA_init: CIA_STAT was 0x%x\n", temp);
 		temp = *(vuip)CIA_IOC_MCR; mb();
 		printk("CIA_init: CIA_MCR was 0x%x\n", temp);
+		temp = *(vuip)CIA_IOC_CIA_CTRL; mb();
+		printk("CIA_init: CIA_CTRL was 0x%x\n", temp);
+		temp = *(vuip)CIA_IOC_ERR_MASK; mb();
+		printk("CIA_init: CIA_ERR_MASK was 0x%x\n", temp);
+		temp = *((vuip)CIA_IOC_PCI_W0_BASE); mb();
+		printk("CIA_init: W0_BASE was 0x%x\n", temp);
+		temp = *((vuip)CIA_IOC_PCI_W1_BASE); mb();
+		printk("CIA_init: W1_BASE was 0x%x\n", temp);
+		temp = *((vuip)CIA_IOC_PCI_W2_BASE); mb();
+		printk("CIA_init: W2_BASE was 0x%x\n", temp);
+		temp = *((vuip)CIA_IOC_PCI_W3_BASE); mb();
+		printk("CIA_init: W3_BASE was 0x%x\n", temp);
 	}
 #endif /* DEBUG_DUMP_REGS */
 
@@ -458,6 +476,70 @@ unsigned long cia_init(unsigned long mem_start, unsigned long mem_end)
 	*(vuip)CIA_IOC_CIA_CTRL = cia_tmp;
 	mb();
 
+#ifdef CONFIG_ALPHA_SRM_SETUP
+	/* check window 0 for enabled and mapped to 0 */
+	if (((*(vuip)CIA_IOC_PCI_W0_BASE & 3) == 1) &&
+	    (*(vuip)CIA_IOC_PCI_T0_BASE == 0))
+	{
+	  CIA_DMA_WIN_BASE = *(vuip)CIA_IOC_PCI_W0_BASE & 0xfff00000U;
+	  CIA_DMA_WIN_SIZE = *(vuip)CIA_IOC_PCI_W0_MASK & 0xfff00000U;
+	  CIA_DMA_WIN_SIZE += 0x00100000U;
+#if 1
+	  printk("cia_init: using Window 0 settings\n");
+	  printk("cia_init: BASE 0x%x MASK 0x%x TRANS 0x%x\n",
+		 *(vuip)CIA_IOC_PCI_W0_BASE,
+		 *(vuip)CIA_IOC_PCI_W0_MASK,
+		 *(vuip)CIA_IOC_PCI_T0_BASE);
+#endif
+	}
+	else  /* check window 1 for enabled and mapped to 0 */
+	if (((*(vuip)CIA_IOC_PCI_W1_BASE & 3) == 1) &&
+	    (*(vuip)CIA_IOC_PCI_T1_BASE == 0))
+	{
+	  CIA_DMA_WIN_BASE = *(vuip)CIA_IOC_PCI_W1_BASE & 0xfff00000U;
+	  CIA_DMA_WIN_SIZE = *(vuip)CIA_IOC_PCI_W1_MASK & 0xfff00000U;
+	  CIA_DMA_WIN_SIZE += 0x00100000U;
+#if 1
+	  printk("cia_init: using Window 1 settings\n");
+	  printk("cia_init: BASE 0x%x MASK 0x%x TRANS 0x%x\n",
+		 *(vuip)CIA_IOC_PCI_W1_BASE,
+		 *(vuip)CIA_IOC_PCI_W1_MASK,
+		 *(vuip)CIA_IOC_PCI_T1_BASE);
+#endif
+	}
+	else  /* check window 2 for enabled and mapped to 0 */
+	if (((*(vuip)CIA_IOC_PCI_W2_BASE & 3) == 1) &&
+	    (*(vuip)CIA_IOC_PCI_T2_BASE == 0))
+	{
+	  CIA_DMA_WIN_BASE = *(vuip)CIA_IOC_PCI_W2_BASE & 0xfff00000U;
+	  CIA_DMA_WIN_SIZE = *(vuip)CIA_IOC_PCI_W2_MASK & 0xfff00000U;
+	  CIA_DMA_WIN_SIZE += 0x00100000U;
+#if 1
+	  printk("cia_init: using Window 2 settings\n");
+	  printk("cia_init: BASE 0x%x MASK 0x%x TRANS 0x%x\n",
+		 *(vuip)CIA_IOC_PCI_W2_BASE,
+		 *(vuip)CIA_IOC_PCI_W2_MASK,
+		 *(vuip)CIA_IOC_PCI_T2_BASE);
+#endif
+	}
+	else  /* check window 3 for enabled and mapped to 0 */
+	if (((*(vuip)CIA_IOC_PCI_W3_BASE & 3) == 1) &&
+	    (*(vuip)CIA_IOC_PCI_T3_BASE == 0))
+	{
+	  CIA_DMA_WIN_BASE = *(vuip)CIA_IOC_PCI_W3_BASE & 0xfff00000U;
+	  CIA_DMA_WIN_SIZE = *(vuip)CIA_IOC_PCI_W3_MASK & 0xfff00000U;
+	  CIA_DMA_WIN_SIZE += 0x00100000U;
+#if 1
+	  printk("cia_init: using Window 3 settings\n");
+	  printk("cia_init: BASE 0x%x MASK 0x%x TRANS 0x%x\n",
+		 *(vuip)CIA_IOC_PCI_W3_BASE,
+		 *(vuip)CIA_IOC_PCI_W3_MASK,
+		 *(vuip)CIA_IOC_PCI_T3_BASE);
+#endif
+	}
+	else  /* we must use our defaults which were pre-initialized... */
+#endif /* SRM_SETUP */
+	{
 	/*
 	 * Set up the PCI->physical memory translation windows.
 	 * For now, windows 1,2 and 3 are disabled.  In the future, we may
@@ -472,6 +554,7 @@ unsigned long cia_init(unsigned long mem_start, unsigned long mem_end)
 	*(vuip)CIA_IOC_PCI_W1_BASE = 0x0;
 	*(vuip)CIA_IOC_PCI_W2_BASE = 0x0;
 	*(vuip)CIA_IOC_PCI_W3_BASE = 0x0;
+	}
 
 	/*
 	 * check ASN in HWRPB for validity, report if bad
@@ -483,28 +566,54 @@ unsigned long cia_init(unsigned long mem_start, unsigned long mem_end)
 	}
 
         /*
-         * Finally, clear the CIA_CFG register, which gets used
+         * Next, clear the CIA_CFG register, which gets used
          *  for PCI Config Space accesses. That is the way
          *  we want to use it, and we do not want to depend on
          *  what ARC or SRM might have left behind...
          */
         {
-#if 0
-		unsigned int cia_cfg = *(vuip)CIA_IOC_CFG; mb();
-		if (cia_cfg) printk("CIA_init: CFG was 0x%x\n", cia_cfg);
-#endif
-		*(vuip)CIA_IOC_CFG = 0; mb();
+          unsigned int cia_cfg = *((vuip)CIA_IOC_CFG); mb();
+          if (cia_cfg) {
+	      printk("CIA_init: CFG was 0x%x\n", cia_cfg);
+	      *((vuip)CIA_IOC_CFG) = 0; mb();
+	  }
         }
  
-#if 0
 	{
-		unsigned int temp;
-		temp = *(vuip)CIA_IOC_CIA_CTRL; mb();
-		printk("CIA_init: CIA_CTRL was 0x%x\n", temp);
-		temp = *(vuip)CIA_IOC_ERR_MASK; mb();
-		printk("CIA_init: CIA_ERR_MASK was 0x%x\n", temp);
-	}
+          unsigned int cia_hae_mem = *((vuip)CIA_IOC_HAE_MEM);
+          unsigned int cia_hae_io = *((vuip)CIA_IOC_HAE_IO);
+#if 0
+	  printk("CIA_init: HAE_MEM was 0x%x\n", cia_hae_mem);
+	  printk("CIA_init: HAE_IO was 0x%x\n", cia_hae_io);
 #endif
+#ifdef CONFIG_ALPHA_SRM_SETUP
+	  /*
+	    sigh... For the SRM setup, unless we know apriori what the HAE
+	    contents will be, we need to setup the arbitrary region bases
+	    so we can test against the range of addresses and tailor the
+	    region chosen for the SPARSE memory access.
+
+	    see include/asm-alpha/cia.h for the SPARSE mem read/write
+	  */
+	  cia_sm_base_r1 = (cia_hae_mem      ) & 0xe0000000UL; /* region 1 */
+	  cia_sm_base_r2 = (cia_hae_mem << 16) & 0xf8000000UL; /* region 2 */
+	  cia_sm_base_r3 = (cia_hae_mem << 24) & 0xfc000000UL; /* region 3 */
+
+	  /*
+	    Set the HAE cache, so that setup_arch() code
+	    will use the SRM setting always. Our readb/writeb
+	    code in cia.h expects never to have to change
+	    the contents of the HAE.
+	   */
+	  hae.cache = cia_hae_mem;
+#else /* SRM_SETUP */
+	  *((vuip)CIA_IOC_HAE_MEM) = 0; mb();
+	  cia_hae_mem = *((vuip)CIA_IOC_HAE_MEM);
+	  *((vuip)CIA_IOC_HAE_IO) = 0; mb();
+	  cia_hae_io = *((vuip)CIA_IOC_HAE_IO);
+#endif /* SRM_SETUP */
+        }
+ 
 	return mem_start;
 }
 
@@ -512,7 +621,7 @@ int cia_pci_clr_err(void)
 {
 	CIA_jd = *(vuip)CIA_IOC_CIA_ERR;
 	DBGM(("CIA_pci_clr_err: CIA ERR after read 0x%x\n", CIA_jd));
-	*(vulp)CIA_IOC_CIA_ERR = 0x0180;
+	*(vuip)CIA_IOC_CIA_ERR = 0x0180;
 	mb();
 	return 0;
 }

arch/alpha/kernel/entry.S

@@ -4,6 +4,7 @@
  * kernel entry-points
  */
 
+#include <linux/config.h>
 #include <asm/system.h>
 
 #define halt	.long PAL_halt
@@ -48,6 +49,8 @@
  * JRP - Save regs 16-18 in a special area of the stack, so that
  * the palcode-provided values are available to the signal handler.
  */
+#if defined(CONFIG_ALPHA_TSUNAMI)
+/* TSUNAMI has no HAE register to save/restore */
 #define SAVE_ALL			\
 	subq	$30,184,$30;		\
 	stq	$0,0($30);		\
@@ -55,6 +58,55 @@
 	stq	$2,16($30);		\
 	stq	$3,24($30);		\
 	stq	$4,32($30);		\
+	stq	$5,40($30);		\
+	stq	$6,48($30);		\
+	stq	$7,56($30);		\
+	stq	$8,64($30);		\
+	stq	$19,72($30);		\
+	stq	$20,80($30);		\
+	stq	$21,88($30);		\
+	stq	$22,96($30);		\
+	stq	$23,104($30);		\
+	stq	$24,112($30);		\
+	stq	$25,120($30);		\
+	stq	$26,128($30);		\
+	stq	$27,136($30);		\
+	stq	$28,144($30);		\
+	stq	$16,160($30);		\
+	stq	$17,168($30);		\
+	stq	$18,176($30)
+
+#define RESTORE_ALL			\
+	ldq	$0,0($30);		\
+	ldq	$1,8($30);		\
+	ldq	$2,16($30);		\
+	ldq	$3,24($30);		\
+	ldq	$4,32($30);		\
+	ldq	$5,40($30);		\
+	ldq	$6,48($30);		\
+	ldq	$7,56($30);		\
+	ldq	$8,64($30);		\
+	ldq	$19,72($30);		\
+	ldq	$20,80($30);		\
+	ldq	$21,88($30);		\
+	ldq	$22,96($30);		\
+	ldq	$23,104($30);		\
+	ldq	$24,112($30);		\
+	ldq	$25,120($30);		\
+	ldq	$26,128($30);		\
+	ldq	$27,136($30);		\
+	ldq	$28,144($30);		\
+	addq	$30,184,$30
+
+#else /* TSUNAMI */
+#define SAVE_ALL			\
+	subq	$30,184,$30;		\
+	stq	$0,0($30);		\
+	stq	$1,8($30);		\
+	stq	$2,16($30);		\
+	stq	$3,24($30);		\
+	stq	$4,32($30);		\
+	stq	$28,144($30);		\
 	lda	$2,hae;			\
 	stq	$5,40($30);		\
 	stq	$6,48($30);		\
@@ -70,7 +122,6 @@
 	stq	$25,120($30);		\
 	stq	$26,128($30);		\
 	stq	$27,136($30);		\
-	stq	$28,144($30);		\
 	stq	$2,152($30);		\
 	stq	$16,160($30);		\
 	stq	$17,168($30);		\
@@ -113,6 +164,8 @@
 	ldq	$28,144($30);		\
 	addq	$30,184,$30
 
+#endif /* TSUNAMI */
+
 .text
 .set noat
 #if defined(__linux__) && !defined(__ELF__)
@@ -508,6 +561,8 @@ sys_clone:
 alpha_switch_to:
 	bsr $1,do_switch_stack
 	call_pal PAL_swpctx
+	lda $16,-2($31)
+	call_pal PAL_tbi
 	bsr $1,undo_switch_stack
 	ret $31,($26),1
 .end alpha_switch_to
@@ -681,6 +736,19 @@ signal_return:
 	br	$31,restore_all
 .end entSys
 
+#ifdef __SMP__
+        .globl  ret_from_smpfork
+.align 3
+.ent ret_from_smpfork
+ret_from_smpfork:
+	.set at
+	stq	$31,scheduler_lock	
+	mb	/* ?????????????????? */
+	br	ret_from_sys_call
+	.set noat
+.end ret_from_smpfork
+#endif /* __SMP__ */
+
 .align 3
 .ent reschedule
 reschedule:

arch/alpha/kernel/head.S

@@ -8,6 +8,7 @@
  */
 
 #define __ASSEMBLY__
+#include <linux/config.h>
 #include <asm/system.h>
 
 #define halt call_pal PAL_halt
@@ -32,6 +33,27 @@ __start:
 	halt
 	.end __start
 
+#ifdef __SMP__
+	.align 3
+	.globl	__start_cpu
+	.ent	__start_cpu
+	/* on entry here from SRM console, the HWPCB of this processor */
+	/* has been loaded, and $27 contains the task pointer */
+__start_cpu:
+	/* first order of business, load the GP */
+	br	$26,1f
+1:	ldgp	$29,0($26)
+	/* We need to get current loaded up with our first task...  */
+	lda	$8,0($27)
+	/* set FEN */
+	lda	$16,1($31)
+	call_pal PAL_wrfen
+	/* ... and then we can start the processor.  */
+	jsr	$26,start_secondary
+	halt
+	.end __start_cpu
+#endif /* __SMP__ */
+
 	.align 3
 	.globl	wrent
 	.ent	wrent

arch/alpha/kernel/lca.c

@@ -6,6 +6,7 @@
  * bios code.
  */
 #include <linux/kernel.h>
+#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/bios32.h>
 #include <linux/pci.h>
@@ -44,6 +45,11 @@
 #define MCHK_K_SIO_IOCHK	0x206	/* all platforms so far */
 #define MCHK_K_DCSR		0x208	/* all but Noname */
 
+#ifdef CONFIG_ALPHA_SRM_SETUP
+unsigned int LCA_DMA_WIN_BASE = LCA_DMA_WIN_BASE_DEFAULT;
+unsigned int LCA_DMA_WIN_SIZE = LCA_DMA_WIN_SIZE_DEFAULT;
+#endif /* SRM_SETUP */
+
 /*
  * Given a bus, device, and function number, compute resulting
  * configuration space address and setup the LCA_IOC_CONF register
@@ -100,11 +106,11 @@ static int mk_conf_addr(unsigned char bus, unsigned char device_fn,
 			return -1;
 		}
 
-		*((vulp) LCA_IOC_CONF) = 0;
+		*(vulp)LCA_IOC_CONF = 0;
 		addr = (1 << (11 + device)) | (func << 8) | where;
 	} else {
 		/* type 1 configuration cycle: */
-		*((vulp) LCA_IOC_CONF) = 1;
+		*(vulp)LCA_IOC_CONF = 1;
 		addr = (bus << 16) | (device_fn << 8) | where;
 	}
 	*pci_addr = addr;
@@ -130,7 +136,7 @@ static unsigned int conf_read(unsigned long addr)
 	value = *(vuip)addr;
 	draina();
 
-	stat0 = *((unsigned long*)LCA_IOC_STAT0);
+	stat0 = *(vulp)LCA_IOC_STAT0;
 	if (stat0 & LCA_IOC_STAT0_ERR) {
 		code = ((stat0 >> LCA_IOC_STAT0_CODE_SHIFT)
 			& LCA_IOC_STAT0_CODE_MASK);
@@ -167,7 +173,7 @@ static void conf_write(unsigned long addr, unsigned int value)
 	*(vuip)addr = value;
 	draina();
 
-	stat0 = *((unsigned long*)LCA_IOC_STAT0);
+	stat0 = *(vulp)LCA_IOC_STAT0;
 	if (stat0 & LCA_IOC_STAT0_ERR) {
 		code = ((stat0 >> LCA_IOC_STAT0_CODE_SHIFT)
 			& LCA_IOC_STAT0_CODE_MASK);
@@ -287,6 +293,40 @@ int pcibios_write_config_dword (unsigned char bus, unsigned char device_fn,
 
 unsigned long lca_init(unsigned long mem_start, unsigned long mem_end)
 {
+#ifdef CONFIG_ALPHA_SRM_SETUP
+	/* check window 0 for enabled and mapped to 0 */
+	if ((*(vulp)LCA_IOC_W_BASE0 & (1UL<<33)) &&
+	    (*(vulp)LCA_IOC_T_BASE0 == 0))
+	{
+	  LCA_DMA_WIN_BASE = *(vulp)LCA_IOC_W_BASE0 & 0xffffffffUL;
+	  LCA_DMA_WIN_SIZE = *(vulp)LCA_IOC_W_MASK0 & 0xffffffffUL;
+	  LCA_DMA_WIN_SIZE += 1;
+#if 1
+	  printk("lca_init: using Window 0 settings\n");
+	  printk("lca_init: BASE 0x%lx MASK 0x%lx TRANS 0x%lx\n",
+		 *(vulp)LCA_IOC_W_BASE0,
+		 *(vulp)LCA_IOC_W_MASK0,
+		 *(vulp)LCA_IOC_T_BASE0);
+#endif
+	}
+	else	/* check window 2 for enabled and mapped to 0 */
+	if ((*(vulp)LCA_IOC_W_BASE1 & (1UL<<33)) &&
+	    (*(vulp)LCA_IOC_T_BASE1 == 0))
+	{
+	  LCA_DMA_WIN_BASE = *(vulp)LCA_IOC_W_BASE1 & 0xffffffffUL;
+	  LCA_DMA_WIN_SIZE = *(vulp)LCA_IOC_W_MASK1 & 0xffffffffUL;
+	  LCA_DMA_WIN_SIZE += 1;
+#if 1
+	  printk("lca_init: using Window 1 settings\n");
+	  printk("lca_init: BASE 0x%lx MASK 0x%lx TRANS 0x%lx\n",
+		 *(vulp)LCA_IOC_W_BASE1,
+		 *(vulp)LCA_IOC_W_MASK1,
+		 *(vulp)LCA_IOC_T_BASE1);
+#endif
+	}
+	else /* we must use our defaults... */
+#endif /* SRM_SETUP */
+	{
 	/*
 	 * Set up the PCI->physical memory translation windows.
 	 * For now, window 1 is disabled.  In the future, we may
@@ -294,9 +334,11 @@ unsigned long lca_init(unsigned long mem_start, unsigned long mem_end)
 	 * goes at 1 GB and is 1 GB large.
 	 */
 	*(vulp)LCA_IOC_W_BASE1 = 0UL<<33;
+
 	*(vulp)LCA_IOC_W_BASE0 = 1UL<<33 | LCA_DMA_WIN_BASE;
 	*(vulp)LCA_IOC_W_MASK0 = LCA_DMA_WIN_SIZE - 1;
 	*(vulp)LCA_IOC_T_BASE0 = 0;
+	}
 
 	/*
 	 * Disable PCI parity for now.  The NCR53c810 chip has

arch/alpha/kernel/process.c

@@ -66,10 +66,49 @@ asmlinkage int sys_sethae(unsigned long hae, unsigned long a1, unsigned long a2,
 	unsigned long a3, unsigned long a4, unsigned long a5,
 	struct pt_regs regs)
 {
+#if !defined(CONFIG_ALPHA_TSUNAMI)
 	(&regs)->hae = hae;
+#endif
 	return 0;
 }
 
+#ifdef __SMP__
+/* This is being executed in task 0 'user space'. */
+#define resched_needed() 1
+int cpu_idle(void *unused)
+{
+	extern volatile int smp_commenced;
+
+	current->priority = -100;
+	while (1) {
+		/*
+		 * tq_scheduler currently assumes we're running in a process
+		 * context (ie that we hold the kernel lock..)
+		 */
+		if (tq_scheduler) {
+			lock_kernel();
+			run_task_queue(&tq_scheduler);
+			unlock_kernel();
+		}
+		/* endless idle loop with no priority at all */
+		current->counter = -100;
+		if (!smp_commenced || resched_needed()) {
+			schedule();
+		}
+	}
+}
+
+asmlinkage int sys_idle(void)
+{
+        if(current->pid != 0)
+                return -EPERM;
+
+        cpu_idle(NULL);
+        return 0;
+}
+
+#else /* __SMP__ */
+
 asmlinkage int sys_idle(void)
 {
 	int ret = -EPERM;
@@ -88,6 +127,12 @@ asmlinkage int sys_idle(void)
 	unlock_kernel();
 	return ret;
 }
+#endif /* __SMP__ */
+
+#if defined(CONFIG_ALPHA_SRM_SETUP)
+extern void reset_for_srm(void);	
+extern unsigned long srm_hae;
+#endif
 
 static void finish_shutdown(void)
 {
@@ -96,8 +141,8 @@ static void finish_shutdown(void)
 	unsigned long flags;
 
 	/* i'm not sure if i really need to disable interrupts here */
-	save_flags(flags);
-	cli();
+	save_and_cli(flags);
+
  	/* reset periodic interrupt frequency */
         CMOS_WRITE(0x26, RTC_FREQ_SELECT);
 
@@ -131,6 +176,10 @@ void machine_restart(char * __unused)
 /*	flags |=  0x0000000000030000UL; *//* this is "warm bootstrap" */
 	cpup->flags = flags;					       
 	mb();						
+#if defined(CONFIG_ALPHA_SRM_SETUP)
+	reset_for_srm();
+	set_hae(srm_hae);
+#endif
 #endif /* SRM */                                        
 
 	finish_shutdown();
@@ -150,6 +199,10 @@ void machine_halt(void)
 	flags |=  0x0000000000040000UL; /* this is "remain halted" */
 	cpup->flags = flags;					       
 	mb();						
+#if defined(CONFIG_ALPHA_SRM_SETUP)
+	reset_for_srm();
+	set_hae(srm_hae);
+#endif
 
 	finish_shutdown();
 #endif /* SRM */                                        
@@ -228,6 +281,7 @@ int alpha_clone(unsigned long clone_flags, unsigned long usp,
 }
 
 extern void ret_from_sys_call(void);
+extern void ret_from_smpfork(void);
 /*
  * Copy an alpha thread..
  *
@@ -258,7 +312,11 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
 	stack = ((struct switch_stack *) regs) - 1;
 	childstack = ((struct switch_stack *) childregs) - 1;
 	*childstack = *stack;
+#ifdef __SMP__
+	childstack->r26 = (unsigned long) ret_from_smpfork;
+#else
 	childstack->r26 = (unsigned long) ret_from_sys_call;
+#endif
 	p->tss.usp = usp;
 	p->tss.ksp = (unsigned long) childstack;
 	p->tss.pal_flags = 1;	/* set FEN, clear everything else */

arch/alpha/kernel/time.c

@@ -82,6 +82,16 @@ void timer_interrupt(int irq, void *dev, struct pt_regs * regs)
 	__u32 now;
 	long nticks;
 
+#ifdef __SMP__
+	extern void smp_percpu_timer_interrupt(struct pt_regs *);
+	extern unsigned int boot_cpu_id;
+	/* when SMP, do this for *all* CPUs, 
+	   but only do the rest for the boot CPU */
+	smp_percpu_timer_interrupt(regs);
+	if (smp_processor_id() != boot_cpu_id)
+	  return;
+#endif
+
 	/*
 	 * Estimate how many ticks have passed since the last update.
 	 * Round the result, .5 to even.  When we loose ticks due to

arch/arm/config.in

@@ -105,17 +105,6 @@ fi
 # fi
 # endmenu
 
-# Conditionally compile in the Uniform CD-ROM driver
-if [ "$CONFIG_BLK_DEV_IDECD" = "y" -o "$CONFIG_BLK_DEV_SR" = "y" ]; then
-  define_bool CONFIG_CDROM y
-else
-  if [ "$CONFIG_BLK_DEV_IDECD" = "m" -o "$CONFIG_BLK_DEV_SR" = "m" ]; then
-    define_bool CONFIG_CDROM m
-  else
-    define_bool CONFIG_CDROM n
-  fi
-fi
-
 source fs/Config.in
 
 source fs/nls/Config.in

arch/arm/defconfig

@@ -169,7 +169,6 @@ CONFIG_PPP=m
 CONFIG_ETHER1=m
 CONFIG_ETHER3=m
 CONFIG_ETHERH=m
-CONFIG_CDROM=y
 
 #
 # Filesystems

arch/i386/defconfig

@@ -214,7 +214,6 @@ CONFIG_EEXPRESS_PRO100=y
 # CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
 #
 # CONFIG_CD_NO_IDESCSI is not set
-CONFIG_CDROM=y
 
 #
 # Filesystems