Commit 5e87325f authored by José Roberto de Souza's avatar José Roberto de Souza Committed by Rodrigo Vivi

drm/i915/psr/cnl: Enable Y-coordinate support in source

For Geminilake and Cannonlake+ the Y-coordinate support must be
enabled in PSR2_CTL too.

Spec: 7713 and 7720

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328223046.16125-5-jose.souza@intel.com
parent aee3bac0
...@@ -4058,6 +4058,8 @@ enum { ...@@ -4058,6 +4058,8 @@ enum {
#define EDP_PSR2_CTL _MMIO(0x6f900) #define EDP_PSR2_CTL _MMIO(0x6f900)
#define EDP_PSR2_ENABLE (1<<31) #define EDP_PSR2_ENABLE (1<<31)
#define EDP_SU_TRACK_ENABLE (1<<30) #define EDP_SU_TRACK_ENABLE (1<<30)
#define EDP_Y_COORDINATE_VALID (1<<26) /* GLK and CNL+ */
#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+ */
#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
#define EDP_PSR2_TP2_TIME_500 (0<<8) #define EDP_PSR2_TP2_TIME_500 (0<<8)
...@@ -7042,6 +7044,7 @@ enum { ...@@ -7042,6 +7044,7 @@ enum {
#define CHICKEN_TRANS_A 0x420c0 #define CHICKEN_TRANS_A 0x420c0
#define CHICKEN_TRANS_B 0x420c4 #define CHICKEN_TRANS_B 0x420c4
#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B) #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
#define VSC_DATA_SEL_SOFTWARE_CONTROL (1<<25) /* GLK and CNL+ */
#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19) #define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
#define DDI_TRAINING_OVERRIDE_VALUE (1<<18) #define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */ #define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
......
...@@ -386,8 +386,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) ...@@ -386,8 +386,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
/* FIXME: selective update is probably totally broken because it doesn't /* FIXME: selective update is probably totally broken because it doesn't
* mesh at all with our frontbuffer tracking. And the hw alone isn't * mesh at all with our frontbuffer tracking. And the hw alone isn't
* good enough. */ * good enough. */
val |= EDP_PSR2_ENABLE | val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
EDP_SU_TRACK_ENABLE; if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
}
if (drm_dp_dpcd_readb(&intel_dp->aux, if (drm_dp_dpcd_readb(&intel_dp->aux,
DP_SYNCHRONIZATION_LATENCY_IN_SINK, DP_SYNCHRONIZATION_LATENCY_IN_SINK,
...@@ -569,8 +571,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp, ...@@ -569,8 +571,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
hsw_psr_setup_aux(intel_dp); hsw_psr_setup_aux(intel_dp);
if (dev_priv->psr.psr2_support) { if (dev_priv->psr.psr2_support) {
u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
| PSR2_ADD_VERTICAL_LINE_COUNT;
if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
| PSR2_ADD_VERTICAL_LINE_COUNT);
else
chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
I915_WRITE(EDP_PSR_DEBUG, I915_WRITE(EDP_PSR_DEBUG,
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment