Commit 5f400639 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amd/pm: make DAL communicate with SMU through unified interfaces

No need to have special handlings for swSMU supported ASICs.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 42b59973
......@@ -242,6 +242,9 @@ struct pp_display_clock_request;
struct pp_clock_levels_with_voltage;
struct pp_clock_levels_with_latency;
struct amd_pp_clocks;
struct pp_smu_wm_range_sets;
struct pp_smu_nv_clock_table;
struct dpm_clocks;
struct amd_pm_funcs {
/* export for dpm on ci and si */
......@@ -336,6 +339,17 @@ struct amd_pm_funcs {
int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
ssize_t (*get_gpu_metrics)(void *handle, void **table);
int (*set_watermarks_for_clock_ranges)(void *handle,
struct pp_smu_wm_range_sets *ranges);
int (*display_disable_memory_clock_switch)(void *handle,
bool disable_memory_clock_switch);
int (*get_max_sustainable_clocks_by_dc)(void *handle,
struct pp_smu_nv_clock_table *max_clocks);
int (*get_uclk_dpm_states)(void *handle,
unsigned int *clock_values_in_khz,
unsigned int *num_states);
int (*get_dpm_clock_table)(void *handle,
struct dpm_clocks *clock_table);
};
struct metrics_table_header {
......
......@@ -1271,16 +1271,6 @@ int smu_get_fan_speed_percent(void *handle, u32 *speed);
int smu_set_fan_speed_percent(void *handle, u32 speed);
int smu_get_fan_speed_rpm(void *handle, uint32_t *speed);
int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
int smu_get_clock_by_type_with_latency(struct smu_context *smu,
enum smu_clk_type clk_type,
struct pp_clock_levels_with_latency *clocks);
int smu_display_clock_voltage_request(struct smu_context *smu,
struct pp_display_clock_request *clock_req);
int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
int smu_set_xgmi_pstate(void *handle,
uint32_t pstate);
......@@ -1315,14 +1305,8 @@ int smu_sys_set_pp_table(void *handle, const char *buf, size_t size);
int smu_get_power_num_states(void *handle, struct pp_states_info *state_info);
enum amd_pm_state_type smu_get_current_power_state(void *handle);
int smu_write_watermarks_table(struct smu_context *smu);
int smu_set_watermarks_for_clock_ranges(
struct smu_context *smu,
struct pp_smu_wm_range_sets *clock_ranges);
/* smu to display interface */
extern int smu_display_configuration_change(struct smu_context *smu, const
struct amd_pp_display_configuration
*display_config);
extern int smu_dpm_set_power_gate(void *handle, uint32_t block_type, bool gate);
extern int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
......@@ -1342,7 +1326,6 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
enum amd_dpm_forced_level smu_get_performance_level(void *handle);
int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level);
int smu_set_display_count(struct smu_context *smu, uint32_t count);
int smu_set_ac_dc(struct smu_context *smu);
int smu_sys_get_pp_feature_mask(void *handle, char *buf);
int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask);
......@@ -1353,16 +1336,6 @@ int smu_set_df_cstate(void *handle,
enum pp_df_cstate state);
int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
struct pp_smu_nv_clock_table *max_clocks);
int smu_get_uclk_dpm_states(struct smu_context *smu,
unsigned int *clock_values_in_khz,
unsigned int *num_states);
int smu_get_dpm_clock_table(struct smu_context *smu,
struct dpm_clocks *clock_table);
int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
ssize_t smu_sys_get_gpu_metrics(void *handle, void **table);
......
......@@ -1519,9 +1519,10 @@ static int smu_resume(void *handle)
return 0;
}
int smu_display_configuration_change(struct smu_context *smu,
int smu_display_configuration_change(void *handle,
const struct amd_pp_display_configuration *display_config)
{
struct smu_context *smu = handle;
int index = 0;
int num_of_active_display = 0;
......@@ -1816,8 +1817,9 @@ int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level)
return ret;
}
int smu_set_display_count(struct smu_context *smu, uint32_t count)
int smu_set_display_count(void *handle, uint32_t count)
{
struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
......@@ -1984,9 +1986,10 @@ int smu_write_watermarks_table(struct smu_context *smu)
return ret;
}
int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
struct pp_smu_wm_range_sets *clock_ranges)
int smu_set_watermarks_for_clock_ranges(void *handle,
struct pp_smu_wm_range_sets *clock_ranges)
{
struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
......@@ -2519,8 +2522,9 @@ int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
return ret;
}
int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
{
struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
......@@ -2535,10 +2539,12 @@ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
return ret;
}
int smu_get_clock_by_type_with_latency(struct smu_context *smu,
enum smu_clk_type clk_type,
int smu_get_clock_by_type_with_latency(void *handle,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_latency *clocks)
{
struct smu_context *smu = handle;
enum smu_clk_type clk_type;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
......@@ -2546,17 +2552,38 @@ int smu_get_clock_by_type_with_latency(struct smu_context *smu,
mutex_lock(&smu->mutex);
if (smu->ppt_funcs->get_clock_by_type_with_latency)
if (smu->ppt_funcs->get_clock_by_type_with_latency) {
switch (type) {
case amd_pp_sys_clock:
clk_type = SMU_GFXCLK;
break;
case amd_pp_mem_clock:
clk_type = SMU_MCLK;
break;
case amd_pp_dcef_clock:
clk_type = SMU_DCEFCLK;
break;
case amd_pp_disp_clock:
clk_type = SMU_DISPCLK;
break;
default:
dev_err(smu->adev->dev, "Invalid clock type!\n");
mutex_unlock(&smu->mutex);
return -EINVAL;
}
ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
}
mutex_unlock(&smu->mutex);
return ret;
}
int smu_display_clock_voltage_request(struct smu_context *smu,
int smu_display_clock_voltage_request(void *handle,
struct pp_display_clock_request *clock_req)
{
struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
......@@ -2573,8 +2600,10 @@ int smu_display_clock_voltage_request(struct smu_context *smu,
}
int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
int smu_display_disable_memory_clock_switch(void *handle,
bool disable_memory_clock_switch)
{
struct smu_context *smu = handle;
int ret = -EINVAL;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
......@@ -2833,9 +2862,10 @@ int smu_mode2_reset(void *handle)
return ret;
}
int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
int smu_get_max_sustainable_clocks_by_dc(void *handle,
struct pp_smu_nv_clock_table *max_clocks)
{
struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
......@@ -2851,10 +2881,11 @@ int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
return ret;
}
int smu_get_uclk_dpm_states(struct smu_context *smu,
int smu_get_uclk_dpm_states(void *handle,
unsigned int *clock_values_in_khz,
unsigned int *num_states)
{
struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
......@@ -2888,9 +2919,10 @@ enum amd_pm_state_type smu_get_current_power_state(void *handle)
return pm_state;
}
int smu_get_dpm_clock_table(struct smu_context *smu,
int smu_get_dpm_clock_table(void *handle,
struct dpm_clocks *clock_table)
{
struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
......@@ -3007,4 +3039,14 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.get_power_profile_mode = smu_get_power_profile_mode,
.force_clock_level = smu_force_ppclk_levels,
.print_clock_levels = smu_print_ppclk_levels,
.get_uclk_dpm_states = smu_get_uclk_dpm_states,
.get_dpm_clock_table = smu_get_dpm_clock_table,
.display_configuration_change = smu_display_configuration_change,
.get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
.display_clock_voltage_request = smu_display_clock_voltage_request,
.set_active_display_count = smu_set_display_count,
.set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
.set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
.display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
.get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
};
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