Commit 5f64e77e authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher

drm/amd/amdgpu: Enable clockgating for UVD5 on Tonga

This patch enables clock gating for the UVD5 block with
Tonga.
Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent be3ecca7
...@@ -1081,7 +1081,7 @@ static int vi_common_early_init(void *handle) ...@@ -1081,7 +1081,7 @@ static int vi_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x3c; adev->external_rev_id = adev->rev_id + 0x3c;
break; break;
case CHIP_TONGA: case CHIP_TONGA:
adev->cg_flags = 0; adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x14; adev->external_rev_id = adev->rev_id + 0x14;
break; break;
......
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