Commit 5fb9cc4d authored by Christian König's avatar Christian König

drm/radeon: apply more strict limits for PLL params v2

Letting post and refernce divider get to big is bad for signal stability.

v2: increase the limit to 210
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
parent 6abc6d5c
...@@ -937,6 +937,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, ...@@ -937,6 +937,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
} }
post_div = post_div_best; post_div = post_div_best;
/* limit reference * post divider to a maximum */
ref_div_max = min(210 / post_div, ref_div_max);
/* get matching reference and feedback divider */ /* get matching reference and feedback divider */
ref_div = max(den / post_div, 1u); ref_div = max(den / post_div, 1u);
fb_div = nom; fb_div = nom;
......
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