Commit 5fe858b5 authored by Linus Torvalds's avatar Linus Torvalds

Merge git://github.com/davem330/sparc

* git://github.com/davem330/sparc:
  sparc64: Force the execute bit in OpenFirmware's translation entries.
  sparc: Make '-p' boot option meaningful again.
  sparc, exec: remove redundant addr_limit assignment
  sparc64: Future proof Niagara cpu detection.
parents 8e8e500f f4142cba
...@@ -43,6 +43,8 @@ ...@@ -43,6 +43,8 @@
#define SUN4V_CHIP_NIAGARA1 0x01 #define SUN4V_CHIP_NIAGARA1 0x01
#define SUN4V_CHIP_NIAGARA2 0x02 #define SUN4V_CHIP_NIAGARA2 0x02
#define SUN4V_CHIP_NIAGARA3 0x03 #define SUN4V_CHIP_NIAGARA3 0x03
#define SUN4V_CHIP_NIAGARA4 0x04
#define SUN4V_CHIP_NIAGARA5 0x05
#define SUN4V_CHIP_UNKNOWN 0xff #define SUN4V_CHIP_UNKNOWN 0xff
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
......
...@@ -66,6 +66,8 @@ static struct xor_block_template xor_block_niagara = { ...@@ -66,6 +66,8 @@ static struct xor_block_template xor_block_niagara = {
((tlb_type == hypervisor && \ ((tlb_type == hypervisor && \
(sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \ (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \ sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \ sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || \
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || \
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) ? \
&xor_block_niagara : \ &xor_block_niagara : \
&xor_block_VIS) &xor_block_VIS)
...@@ -481,6 +481,18 @@ static void __init sun4v_cpu_probe(void) ...@@ -481,6 +481,18 @@ static void __init sun4v_cpu_probe(void)
sparc_pmu_type = "niagara3"; sparc_pmu_type = "niagara3";
break; break;
case SUN4V_CHIP_NIAGARA4:
sparc_cpu_type = "UltraSparc T4 (Niagara4)";
sparc_fpu_type = "UltraSparc T4 integrated FPU";
sparc_pmu_type = "niagara4";
break;
case SUN4V_CHIP_NIAGARA5:
sparc_cpu_type = "UltraSparc T5 (Niagara5)";
sparc_fpu_type = "UltraSparc T5 integrated FPU";
sparc_pmu_type = "niagara5";
break;
default: default:
printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n", printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
prom_cpu_compatible); prom_cpu_compatible);
......
...@@ -325,6 +325,8 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index) ...@@ -325,6 +325,8 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
case SUN4V_CHIP_NIAGARA1: case SUN4V_CHIP_NIAGARA1:
case SUN4V_CHIP_NIAGARA2: case SUN4V_CHIP_NIAGARA2:
case SUN4V_CHIP_NIAGARA3: case SUN4V_CHIP_NIAGARA3:
case SUN4V_CHIP_NIAGARA4:
case SUN4V_CHIP_NIAGARA5:
rover_inc_table = niagara_iterate_method; rover_inc_table = niagara_iterate_method;
break; break;
default: default:
......
...@@ -133,7 +133,7 @@ prom_sun4v_name: ...@@ -133,7 +133,7 @@ prom_sun4v_name:
prom_niagara_prefix: prom_niagara_prefix:
.asciz "SUNW,UltraSPARC-T" .asciz "SUNW,UltraSPARC-T"
prom_sparc_prefix: prom_sparc_prefix:
.asciz "SPARC-T" .asciz "SPARC-"
.align 4 .align 4
prom_root_compatible: prom_root_compatible:
.skip 64 .skip 64
...@@ -396,7 +396,7 @@ sun4v_chip_type: ...@@ -396,7 +396,7 @@ sun4v_chip_type:
or %g1, %lo(prom_cpu_compatible), %g1 or %g1, %lo(prom_cpu_compatible), %g1
sethi %hi(prom_sparc_prefix), %g7 sethi %hi(prom_sparc_prefix), %g7
or %g7, %lo(prom_sparc_prefix), %g7 or %g7, %lo(prom_sparc_prefix), %g7
mov 7, %g3 mov 6, %g3
90: ldub [%g7], %g2 90: ldub [%g7], %g2
ldub [%g1], %g4 ldub [%g1], %g4
cmp %g2, %g4 cmp %g2, %g4
...@@ -408,10 +408,23 @@ sun4v_chip_type: ...@@ -408,10 +408,23 @@ sun4v_chip_type:
sethi %hi(prom_cpu_compatible), %g1 sethi %hi(prom_cpu_compatible), %g1
or %g1, %lo(prom_cpu_compatible), %g1 or %g1, %lo(prom_cpu_compatible), %g1
ldub [%g1 + 7], %g2 ldub [%g1 + 6], %g2
cmp %g2, 'T'
be,pt %xcc, 70f
cmp %g2, 'M'
bne,pn %xcc, 4f
nop
70: ldub [%g1 + 7], %g2
cmp %g2, '3' cmp %g2, '3'
be,pt %xcc, 5f be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA3, %g4 mov SUN4V_CHIP_NIAGARA3, %g4
cmp %g2, '4'
be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA4, %g4
cmp %g2, '5'
be,pt %xcc, 5f
mov SUN4V_CHIP_NIAGARA5, %g4
ba,pt %xcc, 4f ba,pt %xcc, 4f
nop nop
...@@ -543,6 +556,12 @@ niagara_tlb_fixup: ...@@ -543,6 +556,12 @@ niagara_tlb_fixup:
be,pt %xcc, niagara2_patch be,pt %xcc, niagara2_patch
nop nop
cmp %g1, SUN4V_CHIP_NIAGARA3 cmp %g1, SUN4V_CHIP_NIAGARA3
be,pt %xcc, niagara2_patch
nop
cmp %g1, SUN4V_CHIP_NIAGARA4
be,pt %xcc, niagara2_patch
nop
cmp %g1, SUN4V_CHIP_NIAGARA5
be,pt %xcc, niagara2_patch be,pt %xcc, niagara2_patch
nop nop
......
...@@ -380,8 +380,7 @@ void flush_thread(void) ...@@ -380,8 +380,7 @@ void flush_thread(void)
#endif #endif
} }
/* Now, this task is no longer a kernel thread. */ /* This task is no longer a kernel thread. */
current->thread.current_ds = USER_DS;
if (current->thread.flags & SPARC_FLAG_KTHREAD) { if (current->thread.flags & SPARC_FLAG_KTHREAD) {
current->thread.flags &= ~SPARC_FLAG_KTHREAD; current->thread.flags &= ~SPARC_FLAG_KTHREAD;
......
...@@ -368,9 +368,6 @@ void flush_thread(void) ...@@ -368,9 +368,6 @@ void flush_thread(void)
/* Clear FPU register state. */ /* Clear FPU register state. */
t->fpsaved[0] = 0; t->fpsaved[0] = 0;
if (get_thread_current_ds() != ASI_AIUS)
set_fs(USER_DS);
} }
/* It's a bit more tricky when 64-bit tasks are involved... */ /* It's a bit more tricky when 64-bit tasks are involved... */
......
...@@ -137,7 +137,7 @@ static void __init process_switch(char c) ...@@ -137,7 +137,7 @@ static void __init process_switch(char c)
prom_halt(); prom_halt();
break; break;
case 'p': case 'p':
/* Just ignore, this behavior is now the default. */ prom_early_console.flags &= ~CON_BOOT;
break; break;
default: default:
printk("Unknown boot switch (-%c)\n", c); printk("Unknown boot switch (-%c)\n", c);
......
...@@ -106,7 +106,7 @@ static void __init process_switch(char c) ...@@ -106,7 +106,7 @@ static void __init process_switch(char c)
prom_halt(); prom_halt();
break; break;
case 'p': case 'p':
/* Just ignore, this behavior is now the default. */ prom_early_console.flags &= ~CON_BOOT;
break; break;
case 'P': case 'P':
/* Force UltraSPARC-III P-Cache on. */ /* Force UltraSPARC-III P-Cache on. */
...@@ -425,10 +425,14 @@ static void __init init_sparc64_elf_hwcap(void) ...@@ -425,10 +425,14 @@ static void __init init_sparc64_elf_hwcap(void)
else if (tlb_type == hypervisor) { else if (tlb_type == hypervisor) {
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3) sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
cap |= HWCAP_SPARC_BLKINIT; cap |= HWCAP_SPARC_BLKINIT;
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3) sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
cap |= HWCAP_SPARC_N2; cap |= HWCAP_SPARC_N2;
} }
...@@ -452,11 +456,15 @@ static void __init init_sparc64_elf_hwcap(void) ...@@ -452,11 +456,15 @@ static void __init init_sparc64_elf_hwcap(void)
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1) if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
cap |= AV_SPARC_ASI_BLK_INIT; cap |= AV_SPARC_ASI_BLK_INIT;
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3) sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
AV_SPARC_ASI_BLK_INIT | AV_SPARC_ASI_BLK_INIT |
AV_SPARC_POPC); AV_SPARC_POPC);
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3) if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
AV_SPARC_FMAF); AV_SPARC_FMAF);
} }
......
...@@ -511,6 +511,11 @@ static void __init read_obp_translations(void) ...@@ -511,6 +511,11 @@ static void __init read_obp_translations(void)
for (i = 0; i < prom_trans_ents; i++) for (i = 0; i < prom_trans_ents; i++)
prom_trans[i].data &= ~0x0003fe0000000000UL; prom_trans[i].data &= ~0x0003fe0000000000UL;
} }
/* Force execute bit on. */
for (i = 0; i < prom_trans_ents; i++)
prom_trans[i].data |= (tlb_type == hypervisor ?
_PAGE_EXEC_4V : _PAGE_EXEC_4U);
} }
static void __init hypervisor_tlb_lock(unsigned long vaddr, static void __init hypervisor_tlb_lock(unsigned long vaddr,
......
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