Commit 6068e6d7 authored by Robert Hancock's avatar Robert Hancock Committed by Jakub Kicinski

net: dsa: microchip: remove KSZ9477 PHY errata handling

The KSZ9477 PHY errata handling code has now been moved into the Micrel
PHY driver, so it is no longer needed inside the DSA switch driver.
Remove it.
Signed-off-by: default avatarRobert Hancock <robert.hancock@calian.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Reviewed-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 26dd2974
......@@ -889,62 +889,6 @@ static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
return interface;
}
static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
u8 dev_addr, u16 reg_addr, u16 val)
{
ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr));
ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr));
ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
}
static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
{
/* Apply PHY settings to address errata listed in
* KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
* Silicon Errata and Data Sheet Clarification documents:
*
* Register settings are needed to improve PHY receive performance
*/
ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
/* Transmit waveform amplitude can be improved
* (1000BASE-T, 100BASE-TX, 10BASE-Te)
*/
ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
/* Energy Efficient Ethernet (EEE) feature select must
* be manually disabled (except on KSZ8565 which is 100Mbit)
*/
if (dev->info->gbit_capable[port])
ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
/* Register settings are required to meet data sheet
* supply current specifications
*/
ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
}
void ksz9477_get_caps(struct ksz_device *dev, int port,
struct phylink_config *config)
{
......@@ -1029,20 +973,10 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
/* enable 802.1p priority */
ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
if (dev->info->internal_phy[port]) {
/* do not force flow control */
ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
false);
if (dev->info->phy_errata_9477)
ksz9477_phy_errata_setup(dev, port);
} else {
/* force flow control */
ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
true);
}
/* force flow control for non-PHY ports only */
ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
!dev->info->internal_phy[port]);
if (cpu_port)
member = dsa_user_ports(ds);
......
......@@ -1270,7 +1270,6 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.tc_cbs_supported = true,
.tc_ets_supported = true,
.ops = &ksz9477_dev_ops,
.phy_errata_9477 = true,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
......@@ -1303,7 +1302,6 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.port_nirqs = 2,
.num_tx_queues = 4,
.ops = &ksz9477_dev_ops,
.phy_errata_9477 = true,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
......@@ -1336,7 +1334,6 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.port_nirqs = 2,
.num_tx_queues = 4,
.ops = &ksz9477_dev_ops,
.phy_errata_9477 = true,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
......@@ -1423,7 +1420,6 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.tc_cbs_supported = true,
.tc_ets_supported = true,
.ops = &ksz9477_dev_ops,
.phy_errata_9477 = true,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
......
......@@ -60,7 +60,6 @@ struct ksz_chip_data {
bool tc_cbs_supported;
bool tc_ets_supported;
const struct ksz_dev_ops *ops;
bool phy_errata_9477;
bool ksz87xx_eee_link_erratum;
const struct ksz_mib_names *mib_names;
int mib_cnt;
......
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