Commit 609a097f authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'v5.18-rockchip-dtsfixes1' of...

Merge tag 'v5.18-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes

Fixes for the mass-production version of BananaPi R2-Pro.
The mass market version received some changes compared to
preproduction versions and especially the io-domain setting
could affect the lifespan of the board if the wrong dt
gets booted on it.

* tag 'v5.18-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Add gmac1 and change network settings of bpi-r2-pro
  arm64: dts: rockchip: Change io-domains of bpi-r2-pro

Link: https://lore.kernel.org/r/2300256.NG923GbCHz@philSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents e81c07e2 77047ed7
...@@ -16,6 +16,7 @@ / { ...@@ -16,6 +16,7 @@ / {
aliases { aliases {
ethernet0 = &gmac0; ethernet0 = &gmac0;
ethernet1 = &gmac1;
mmc0 = &sdmmc0; mmc0 = &sdmmc0;
mmc1 = &sdhci; mmc1 = &sdhci;
}; };
...@@ -78,7 +79,6 @@ &gmac0 { ...@@ -78,7 +79,6 @@ &gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
clock_in_out = "input"; clock_in_out = "input";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii"; phy-mode = "rgmii";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim pinctrl-0 = <&gmac0_miim
...@@ -90,8 +90,38 @@ &gmac0_rgmii_clk ...@@ -90,8 +90,38 @@ &gmac0_rgmii_clk
snps,reset-active-low; snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */ /* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>; snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x4f>;
rx_delay = <0x0f>;
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x3c>; tx_delay = <0x3c>;
rx_delay = <0x2f>; rx_delay = <0x2f>;
status = "okay"; status = "okay";
}; };
...@@ -315,8 +345,8 @@ &i2c5 { ...@@ -315,8 +345,8 @@ &i2c5 {
status = "disabled"; status = "disabled";
}; };
&mdio0 { &mdio1 {
rgmii_phy0: ethernet-phy@0 { rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>; reg = <0x0>;
}; };
...@@ -345,9 +375,9 @@ &pmu_io_domains { ...@@ -345,9 +375,9 @@ &pmu_io_domains {
pmuio2-supply = <&vcc3v3_pmu>; pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>; vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>; vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>; vccio4-supply = <&vcc_3v3>;
vccio5-supply = <&vcc_3v3>; vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_3v3>; vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>; vccio7-supply = <&vcc_3v3>;
status = "okay"; status = "okay";
}; };
......
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