Commit 60d93f64 authored by Enric Balletbo i Serra's avatar Enric Balletbo i Serra Committed by Matthias Brugger

soc: mediatek: pm-domains: Add a power domain names for mt8167

Add the power domains names for the mt8167 SoC.

Fixes: 207f13b4 ("soc: mediatek: pm-domains: Add support for mt8167")
Signed-off-by: default avatarEnric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: default avatarHsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210225175000.824661-4-enric.balletbo@collabora.comSigned-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 3edc01bc
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
[MT8167_POWER_DOMAIN_MM] = { [MT8167_POWER_DOMAIN_MM] = {
.name = "mm",
.sta_mask = PWR_STATUS_DISP, .sta_mask = PWR_STATUS_DISP,
.ctl_offs = SPM_DIS_PWR_CON, .ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8), .sram_pdn_bits = GENMASK(11, 8),
...@@ -26,6 +27,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { ...@@ -26,6 +27,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.caps = MTK_SCPD_ACTIVE_WAKEUP, .caps = MTK_SCPD_ACTIVE_WAKEUP,
}, },
[MT8167_POWER_DOMAIN_VDEC] = { [MT8167_POWER_DOMAIN_VDEC] = {
.name = "vdec",
.sta_mask = PWR_STATUS_VDEC, .sta_mask = PWR_STATUS_VDEC,
.ctl_offs = SPM_VDE_PWR_CON, .ctl_offs = SPM_VDE_PWR_CON,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
...@@ -33,6 +35,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { ...@@ -33,6 +35,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.caps = MTK_SCPD_ACTIVE_WAKEUP, .caps = MTK_SCPD_ACTIVE_WAKEUP,
}, },
[MT8167_POWER_DOMAIN_ISP] = { [MT8167_POWER_DOMAIN_ISP] = {
.name = "isp",
.sta_mask = PWR_STATUS_ISP, .sta_mask = PWR_STATUS_ISP,
.ctl_offs = SPM_ISP_PWR_CON, .ctl_offs = SPM_ISP_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8), .sram_pdn_bits = GENMASK(11, 8),
...@@ -40,6 +43,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { ...@@ -40,6 +43,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.caps = MTK_SCPD_ACTIVE_WAKEUP, .caps = MTK_SCPD_ACTIVE_WAKEUP,
}, },
[MT8167_POWER_DOMAIN_MFG_ASYNC] = { [MT8167_POWER_DOMAIN_MFG_ASYNC] = {
.name = "mfg_async",
.sta_mask = MT8167_PWR_STATUS_MFG_ASYNC, .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
.ctl_offs = SPM_MFG_ASYNC_PWR_CON, .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
.sram_pdn_bits = 0, .sram_pdn_bits = 0,
...@@ -50,18 +54,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { ...@@ -50,18 +54,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
}, },
}, },
[MT8167_POWER_DOMAIN_MFG_2D] = { [MT8167_POWER_DOMAIN_MFG_2D] = {
.name = "mfg_2d",
.sta_mask = MT8167_PWR_STATUS_MFG_2D, .sta_mask = MT8167_PWR_STATUS_MFG_2D,
.ctl_offs = SPM_MFG_2D_PWR_CON, .ctl_offs = SPM_MFG_2D_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8), .sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12), .sram_pdn_ack_bits = GENMASK(15, 12),
}, },
[MT8167_POWER_DOMAIN_MFG] = { [MT8167_POWER_DOMAIN_MFG] = {
.name = "mfg",
.sta_mask = PWR_STATUS_MFG, .sta_mask = PWR_STATUS_MFG,
.ctl_offs = SPM_MFG_PWR_CON, .ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8), .sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12), .sram_pdn_ack_bits = GENMASK(15, 12),
}, },
[MT8167_POWER_DOMAIN_CONN] = { [MT8167_POWER_DOMAIN_CONN] = {
.name = "conn",
.sta_mask = PWR_STATUS_CONN, .sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON, .ctl_offs = SPM_CONN_PWR_CON,
.sram_pdn_bits = GENMASK(8, 8), .sram_pdn_bits = GENMASK(8, 8),
......
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