can: mcp251xfd: ring: prepare to change order of TX and RX FIFOs
This patch improves the initialization of the TX and RX rings. The initialization functions are now called with pointers to the next free address (in the on chip RAM) and next free hardware FIFO. The rings are initialized using these values and the pointers are modified to point to the next free elements. This means the order of the mcp251xfd_ring_init_*() functions specifies the order of the rings in the hardware FIFO. This makes it possible to change the order of the TX and RX FIFOs, which is done in the next patch. This gives the opportunity to minimize the number of SPI transfers in the IRQ handler. The read of the IRQ status register and RX FIFO status registers can be combined into single SPI transfer. If the RX ring uses FIFO 1, the overall length of the transfer is smaller than in the original layout, where the RX FIFO comes after the TX FIFO. Link: https://lore.kernel.org/all/20220217103826.2299157-4-mkl@pengutronix.deSigned-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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