Commit 62169799 authored by Douglas Anderson's avatar Douglas Anderson Committed by Kleber Sacilotto de Souza

clk: rockchip: Don't yell about bad mmc phases when getting

BugLink: https://bugs.launchpad.net/bugs/1845405

commit 6943b839 upstream.

At boot time, my rk3288-veyron devices yell with 8 lines that look
like this:
  [    0.000000] rockchip_mmc_get_phase: invalid clk rate

This is because the clock framework at clk_register() time tries to
get the phase but we don't have a parent yet.

While the errors appear to be harmless they are still ugly and, in
general, we don't want yells like this in the log unless they are
important.

There's no real reason to be yelling here.  We can still return
-EINVAL to indicate that the phase makes no sense without a parent.
If someone really tries to do tuning and the clock is reported as 0
then we'll see the yells in rockchip_mmc_set_phase().

Fixes: 4bf59902 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero")
Signed-off-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarConnor Kuehl <connor.kuehl@canonical.com>
Signed-off-by: default avatarKleber Sacilotto de Souza <kleber.souza@canonical.com>
parent 8b2376d1
...@@ -61,10 +61,8 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw) ...@@ -61,10 +61,8 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
u32 delay_num = 0; u32 delay_num = 0;
/* See the comment for rockchip_mmc_set_phase below */ /* See the comment for rockchip_mmc_set_phase below */
if (!rate) { if (!rate)
pr_err("%s: invalid clk rate\n", __func__);
return -EINVAL; return -EINVAL;
}
raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
......
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