Commit 6241bf6a authored by Felix Fietkau's avatar Felix Fietkau Committed by Ralf Baechle

MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs

AR913x, AR724x and AR933x are the only SoCs where the
ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c
Invert the logic to make the code compatible with AR95xx
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
Cc: albeu@free.fr
Cc: sergei.shtylyov@cogentembedded.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13257/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent bad50d79
...@@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void) ...@@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void)
{ {
ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
AR71XX_DDR_CTRL_SIZE); AR71XX_DDR_CTRL_SIZE);
if (soc_is_ar71xx() || soc_is_ar934x()) { if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
} else {
ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c; ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
ath79_ddr_pci_win_base = 0; ath79_ddr_pci_win_base = 0;
} else {
ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
} }
} }
EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
......
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