Commit 6357b75a authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu: disable uvd and vce clockgating on Fiji

Doesn't work properly yet.
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarSonny Jiang <sonny.jiang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dba280b2
...@@ -1443,8 +1443,7 @@ static int vi_common_early_init(void *handle) ...@@ -1443,8 +1443,7 @@ static int vi_common_early_init(void *handle)
break; break;
case CHIP_FIJI: case CHIP_FIJI:
adev->has_uvd = true; adev->has_uvd = true;
adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG | adev->cg_flags = 0;
AMDGPU_CG_SUPPORT_VCE_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x3c; adev->external_rev_id = adev->rev_id + 0x3c;
break; break;
......
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