Commit 6391030d authored by Rob Clark's avatar Rob Clark

drm/msm/adreno: Remove redundant gmem size param

Even in the ocmem case, the allocated ocmem buffer size should match the
requested size.

v2: Move stray hunk to previous patch, make OCMEM size mismatch an error
    condition.
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549759/
parent 832ee64d
...@@ -205,7 +205,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu) ...@@ -205,7 +205,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT); A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT);
for (i = 3; i <= 5; i++) for (i = 3; i <= 5; i++)
if ((SZ_16K << i) == adreno_gpu->gmem) if ((SZ_16K << i) == adreno_gpu->info->gmem)
break; break;
gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i); gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i);
......
...@@ -749,7 +749,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) ...@@ -749,7 +749,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO,
0x00100000 + adreno_gpu->gmem - 1); 0x00100000 + adreno_gpu->info->gmem - 1);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) || if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
......
...@@ -1270,7 +1270,7 @@ static int hw_init(struct msm_gpu *gpu) ...@@ -1270,7 +1270,7 @@ static int hw_init(struct msm_gpu *gpu)
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000); gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000);
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX,
0x00100000 + adreno_gpu->gmem - 1); 0x00100000 + adreno_gpu->info->gmem - 1);
} }
gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
......
...@@ -320,7 +320,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, ...@@ -320,7 +320,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
*value = adreno_gpu->info->revn; *value = adreno_gpu->info->revn;
return 0; return 0;
case MSM_PARAM_GMEM_SIZE: case MSM_PARAM_GMEM_SIZE:
*value = adreno_gpu->gmem; *value = adreno_gpu->info->gmem;
return 0; return 0;
case MSM_PARAM_GMEM_BASE: case MSM_PARAM_GMEM_BASE:
*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
...@@ -1041,14 +1041,16 @@ int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, ...@@ -1041,14 +1041,16 @@ int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
return PTR_ERR(ocmem); return PTR_ERR(ocmem);
} }
ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem); ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->info->gmem);
if (IS_ERR(ocmem_hdl)) if (IS_ERR(ocmem_hdl))
return PTR_ERR(ocmem_hdl); return PTR_ERR(ocmem_hdl);
adreno_ocmem->ocmem = ocmem; adreno_ocmem->ocmem = ocmem;
adreno_ocmem->base = ocmem_hdl->addr; adreno_ocmem->base = ocmem_hdl->addr;
adreno_ocmem->hdl = ocmem_hdl; adreno_ocmem->hdl = ocmem_hdl;
adreno_gpu->gmem = ocmem_hdl->len;
if (WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem))
return -ENOMEM;
return 0; return 0;
} }
...@@ -1097,7 +1099,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, ...@@ -1097,7 +1099,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
adreno_gpu->funcs = funcs; adreno_gpu->funcs = funcs;
adreno_gpu->info = adreno_info(config->rev); adreno_gpu->info = adreno_info(config->rev);
adreno_gpu->gmem = adreno_gpu->info->gmem;
adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->revn = adreno_gpu->info->revn;
adreno_gpu->rev = *rev; adreno_gpu->rev = *rev;
......
...@@ -77,7 +77,6 @@ struct adreno_gpu { ...@@ -77,7 +77,6 @@ struct adreno_gpu {
struct msm_gpu base; struct msm_gpu base;
struct adreno_rev rev; struct adreno_rev rev;
const struct adreno_info *info; const struct adreno_info *info;
uint32_t gmem; /* actual gmem size */
uint32_t revn; /* numeric revision name */ uint32_t revn; /* numeric revision name */
uint16_t speedbin; uint16_t speedbin;
const struct adreno_gpu_funcs *funcs; const struct adreno_gpu_funcs *funcs;
......
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