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Commit 63b34416 authored by Tony Lindgren's avatar Tony Lindgren
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ARM: dts: Configure interconnect target module for omap4 dss 

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty until the child
devices are probing with ti-sysc interconnect driver.

The display subsystem (DSS) is in a 16MB interconnect target module
mapped to l4 and l3 buses. We are only using the l3 port as recommended
by the TRM. So there is no need to configure l4 ranges like we've done
for l4 ABE instance for example.

Initially let's just update the top level dss node to probe with ti-sysc
interconnect target module driver. The child nodes are still children
of dispc, only the node indentation changes for them now along with
using the reg range provided by top level dss.

Let's also add add a note about using only the l3 access without l4
as noted in the TRM.

Cc: Jyri Sarha <jsarha@ti.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Sebastian Reichel <sre@kernel.org>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent b2745d92
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Showing with 96 additions and 75 deletions
arch/arm/boot/dts/omap4-l4.dtsi
View file @ 63b34416
...@@ -1529,6 +1529,7 @@ timer9: timer@0 { ...@@ -1529,6 +1529,7 @@ timer9: timer@0 {
}; };
}; };
/* Unused DSS L4 access, see L3 instead */
target-module@40000 { /* 0x48040000, ap 13 0a.0 */ target-module@40000 { /* 0x48040000, ap 13 0a.0 */
compatible = "ti,sysc"; compatible = "ti,sysc";
status = "disabled"; status = "disabled";
......
arch/arm/boot/dts/omap4.dtsi
View file @ 63b34416
...@@ -415,87 +415,107 @@ target-module@56000000 { ...@@ -415,87 +415,107 @@ target-module@56000000 {
*/ */
}; };
dss: dss@58000000 { /*
compatible = "ti,omap4-dss"; * DSS is only using l3 mapping without l4 as noted in the TRM
reg = <0x58000000 0x80>; * "10.1.3 DSS Register Manual" for omap4460.
status = "disabled"; */
target-module@58000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dss_core"; ti,hwmods = "dss_core";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; reg = <0x58000000 4>,
clock-names = "fck"; <0x58000014 4>;
reg-names = "rev", "syss";
ti,syss-mask = <1>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges; ranges = <0 0x58000000 0x1000000>;
dispc@58001000 {
compatible = "ti,omap4-dispc";
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
rfbi: encoder@58002000 {
compatible = "ti,omap4-rfbi";
reg = <0x58002000 0x1000>;
status = "disabled";
ti,hwmods = "dss_rfbi";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
clock-names = "fck", "ick";
};
venc: encoder@58003000 { dss: dss@0 {
compatible = "ti,omap4-venc"; compatible = "ti,omap4-dss";
reg = <0x58003000 0x1000>; reg = <0 0x80>;
status = "disabled"; status = "disabled";
ti,hwmods = "dss_venc"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck"; clock-names = "fck";
}; #address-cells = <1>;
#size-cells = <1>;
dsi1: encoder@58004000 { ranges = <0 0 0x1000000>;
compatible = "ti,omap4-dsi";
reg = <0x58004000 0x200>, dispc@1000 {
<0x58004200 0x40>, compatible = "ti,omap4-dispc";
<0x58004300 0x20>; reg = <0x1000 0x1000>;
reg-names = "proto", "phy", "pll"; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "dss_dispc";
status = "disabled"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
ti,hwmods = "dss_dsi1"; clock-names = "fck";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, };
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk"; rfbi: encoder@2000 {
}; compatible = "ti,omap4-rfbi";
reg = <0x2000 0x1000>;
dsi2: encoder@58005000 { status = "disabled";
compatible = "ti,omap4-dsi"; ti,hwmods = "dss_rfbi";
reg = <0x58005000 0x200>, clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
<0x58005200 0x40>, clock-names = "fck", "ick";
<0x58005300 0x20>; };
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; venc: encoder@3000 {
status = "disabled"; compatible = "ti,omap4-venc";
ti,hwmods = "dss_dsi2"; reg = <0x3000 0x1000>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, status = "disabled";
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; ti,hwmods = "dss_venc";
clock-names = "fck", "sys_clk"; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
}; clock-names = "fck";
};
hdmi: encoder@58006000 {
compatible = "ti,omap4-hdmi"; dsi1: encoder@4000 {
reg = <0x58006000 0x200>, compatible = "ti,omap4-dsi";
<0x58006200 0x100>, reg = <0x4000 0x200>,
<0x58006300 0x100>, <0x4200 0x40>,
<0x58006400 0x1000>; <0x4300 0x20>;
reg-names = "wp", "pll", "phy", "core"; reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
ti,hwmods = "dss_hdmi"; ti,hwmods = "dss_dsi1";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk"; clock-names = "fck", "sys_clk";
dmas = <&sdma 76>; };
dma-names = "audio_tx";
dsi2: encoder@5000 {
compatible = "ti,omap4-dsi";
reg = <0x5000 0x200>,
<0x5200 0x40>,
<0x5300 0x20>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi2";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
hdmi: encoder@6000 {
compatible = "ti,omap4-hdmi";
reg = <0x6000 0x200>,
<0x6200 0x100>,
<0x6300 0x100>,
<0x6400 0x1000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
};
}; };
}; };
}; };
......
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