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Commit 64128ad6 authored by James Simmons's avatar James Simmons
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Supports more NVIDIA cards.

parent 127d7564
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Showing with 54 additions and 11 deletions
drivers/video/riva/fbdev.c
View file @ 64128ad6
...@@ -54,7 +54,7 @@ ...@@ -54,7 +54,7 @@
#include "../fbcon-accel.h" #include "../fbcon-accel.h"
/* version number of this driver */ /* version number of this driver */
#define RIVAFB_VERSION "0.9.2a" #define RIVAFB_VERSION "0.9.3"
/* ------------------------------------------------------------------------- * /* ------------------------------------------------------------------------- *
* *
...@@ -127,6 +127,11 @@ enum riva_chips { ...@@ -127,6 +127,11 @@ enum riva_chips {
CH_GEFORCE2_GTS, CH_GEFORCE2_GTS,
CH_GEFORCE2_ULTRA, CH_GEFORCE2_ULTRA,
CH_QUADRO2_PRO, CH_QUADRO2_PRO,
CH_GEFORCE2_GO,
CH_GEFORCE3,
CH_GEFORCE3_1,
CH_GEFORCE3_2,
CH_QUADRO_DDC
}; };
/* directly indexed by riva_chips enum, above */ /* directly indexed by riva_chips enum, above */
...@@ -149,6 +154,11 @@ static struct riva_chip_info { ...@@ -149,6 +154,11 @@ static struct riva_chip_info {
{ "GeForce2-GTS", NV_ARCH_10}, { "GeForce2-GTS", NV_ARCH_10},
{ "GeForce2-ULTRA", NV_ARCH_10}, { "GeForce2-ULTRA", NV_ARCH_10},
{ "Quadro2-PRO", NV_ARCH_10}, { "Quadro2-PRO", NV_ARCH_10},
{ "GeForce2-Go", NV_ARCH_10},
{ "GeForce3", NV_ARCH_20},
{ "GeForce3 Ti 200", NV_ARCH_20},
{ "GeForce3 Ti 500", NV_ARCH_20},
{ "Quadro DDC", NV_ARCH_20}
}; };
static struct pci_device_id rivafb_pci_tbl[] __devinitdata = { static struct pci_device_id rivafb_pci_tbl[] __devinitdata = {
...@@ -186,6 +196,16 @@ static struct pci_device_id rivafb_pci_tbl[] __devinitdata = { ...@@ -186,6 +196,16 @@ static struct pci_device_id rivafb_pci_tbl[] __devinitdata = {
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_ULTRA }, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_ULTRA },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO }, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GO },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_1 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_2 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO_DDC },
{ 0, } /* terminate list */ { 0, } /* terminate list */
}; };
MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
...@@ -1521,6 +1541,7 @@ static int __devinit rivafb_init_one(struct pci_dev *pd, ...@@ -1521,6 +1541,7 @@ static int __devinit rivafb_init_one(struct pci_dev *pd,
break; break;
case NV_ARCH_04: case NV_ARCH_04:
case NV_ARCH_10: case NV_ARCH_10:
case NV_ARCH_20:
/* riva_hw.c now doesn't distinguish between TNT & TNT2 */ /* riva_hw.c now doesn't distinguish between TNT & TNT2 */
default_par->riva.PCRTC = (unsigned *)(default_par->ctrl_base + 0x00600000); default_par->riva.PCRTC = (unsigned *)(default_par->ctrl_base + 0x00600000);
default_par->riva.PRAMIN = (unsigned *)(default_par->ctrl_base + 0x00710000); default_par->riva.PRAMIN = (unsigned *)(default_par->ctrl_base + 0x00710000);
...@@ -1558,7 +1579,7 @@ static int __devinit rivafb_init_one(struct pci_dev *pd, ...@@ -1558,7 +1579,7 @@ static int __devinit rivafb_init_one(struct pci_dev *pd,
pci_set_drvdata(pd, info); pci_set_drvdata(pd, info);
printk(KERN_INFO PFX printk(KERN_INFO PFX
"PCI nVidia NV%d framebuffer ver %s (%s, %dMB @ 0x%lX)\n", "PCI nVidia NV%x framebuffer ver %s (%s, %dMB @ 0x%lX)\n",
default_par->riva.Architecture, default_par->riva.Architecture,
RIVAFB_VERSION, RIVAFB_VERSION,
info->fix.id, info->fix.id,
......
drivers/video/riva/riva_hw.c
View file @ 64128ad6
...@@ -1220,6 +1220,7 @@ static void CalcStateExt ...@@ -1220,6 +1220,7 @@ static void CalcStateExt
state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
break; break;
case NV_ARCH_10: case NV_ARCH_10:
case NV_ARCH_20:
nv10UpdateArbitrationSettings(VClk, nv10UpdateArbitrationSettings(VClk,
pixelDepth * 8, pixelDepth * 8,
&(state->arbitration0), &(state->arbitration0),
...@@ -1285,6 +1286,7 @@ static void UpdateFifoState ...@@ -1285,6 +1286,7 @@ static void UpdateFifoState
chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]); chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
break; break;
case NV_ARCH_10: case NV_ARCH_10:
case NV_ARCH_20:
/* /*
* Initialize state for the RivaTriangle3D05 routines. * Initialize state for the RivaTriangle3D05 routines.
*/ */
...@@ -1393,6 +1395,7 @@ static void LoadStateExt ...@@ -1393,6 +1395,7 @@ static void LoadStateExt
chip->PGRAPH[0x0000067C/4] = state->pitch3; chip->PGRAPH[0x0000067C/4] = state->pitch3;
break; break;
case NV_ARCH_10: case NV_ARCH_10:
case NV_ARCH_20:
LOAD_FIXED_STATE(nv10,PFIFO); LOAD_FIXED_STATE(nv10,PFIFO);
LOAD_FIXED_STATE(nv10,PRAMIN); LOAD_FIXED_STATE(nv10,PRAMIN);
LOAD_FIXED_STATE(nv10,PGRAPH); LOAD_FIXED_STATE(nv10,PGRAPH);
...@@ -1421,15 +1424,31 @@ static void LoadStateExt ...@@ -1421,15 +1424,31 @@ static void LoadStateExt
chip->Tri03 = 0L; chip->Tri03 = 0L;
break; break;
} }
chip->PGRAPH[0x00000640/4] = state->offset0;
chip->PGRAPH[0x00000644/4] = state->offset1; if (chip->Architecture == NV_ARCH_10) {
chip->PGRAPH[0x00000648/4] = state->offset2; chip->PGRAPH[0x00000640/4] = state->offset0;
chip->PGRAPH[0x0000064C/4] = state->offset3; chip->PGRAPH[0x00000644/4] = state->offset1;
chip->PGRAPH[0x00000670/4] = state->pitch0; chip->PGRAPH[0x00000648/4] = state->offset2;
chip->PGRAPH[0x00000674/4] = state->pitch1; chip->PGRAPH[0x0000064C/4] = state->offset3;
chip->PGRAPH[0x00000678/4] = state->pitch2; chip->PGRAPH[0x00000670/4] = state->pitch0;
chip->PGRAPH[0x0000067C/4] = state->pitch3; chip->PGRAPH[0x00000674/4] = state->pitch1;
chip->PGRAPH[0x00000680/4] = state->pitch3; chip->PGRAPH[0x00000678/4] = state->pitch2;
chip->PGRAPH[0x0000067C/4] = state->pitch3;
chip->PGRAPH[0x00000680/4] = state->pitch3;
} else {
chip->PGRAPH[0x00000820/4] = state->offset0;
chip->PGRAPH[0x00000824/4] = state->offset1;
chip->PGRAPH[0x00000828/4] = state->offset2;
chip->PGRAPH[0x0000082C/4] = state->offset3;
chip->PGRAPH[0x00000850/4] = state->pitch0;
chip->PGRAPH[0x00000854/4] = state->pitch1;
chip->PGRAPH[0x00000858/4] = state->pitch2;
chip->PGRAPH[0x0000085C/4] = state->pitch3;
chip->PGRAPH[0x00000860/4] = state->pitch3;
chip->PGRAPH[0x00000864/4] = state->pitch3;
chip->PGRAPH[0x000009A4/4] = chip->PFB[0x00000200/4];
chip->PGRAPH[0x000009A8/4] = chip->PFB[0x00000204/4];
}
chip->PGRAPH[0x00000B00/4] = chip->PFB[0x00000240/4]; chip->PGRAPH[0x00000B00/4] = chip->PFB[0x00000240/4];
chip->PGRAPH[0x00000B04/4] = chip->PFB[0x00000244/4]; chip->PGRAPH[0x00000B04/4] = chip->PFB[0x00000244/4];
chip->PGRAPH[0x00000B08/4] = chip->PFB[0x00000248/4]; chip->PGRAPH[0x00000B08/4] = chip->PFB[0x00000248/4];
...@@ -1607,6 +1626,7 @@ static void UnloadStateExt ...@@ -1607,6 +1626,7 @@ static void UnloadStateExt
state->pitch3 = chip->PGRAPH[0x0000067C/4]; state->pitch3 = chip->PGRAPH[0x0000067C/4];
break; break;
case NV_ARCH_10: case NV_ARCH_10:
case NV_ARCH_20:
state->offset0 = chip->PGRAPH[0x00000640/4]; state->offset0 = chip->PGRAPH[0x00000640/4];
state->offset1 = chip->PGRAPH[0x00000644/4]; state->offset1 = chip->PGRAPH[0x00000644/4];
state->offset2 = chip->PGRAPH[0x00000648/4]; state->offset2 = chip->PGRAPH[0x00000648/4];
......
drivers/video/riva/riva_hw.h
View file @ 64128ad6
...@@ -74,6 +74,8 @@ typedef unsigned int U032; ...@@ -74,6 +74,8 @@ typedef unsigned int U032;
#define NV_ARCH_03 0x03 #define NV_ARCH_03 0x03
#define NV_ARCH_04 0x04 #define NV_ARCH_04 0x04
#define NV_ARCH_10 0x10 #define NV_ARCH_10 0x10
#define NV_ARCH_20 0x20
/***************************************************************************\ /***************************************************************************\
* * * *
* FIFO registers. * * FIFO registers. *
......
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