Commit 642aa663 authored by Jürgen Schindele's avatar Jürgen Schindele Committed by Russell King

[ARM] 5204/1: Trizeps4 SOM update

- use MFP-API for GPIO
- support TRIZEPS4WL module
- cleanups
Signed-off-by: default avatarJrgen Schindele <linux@schindele.name>
Acked-by: default avatarEric Miao <eric.miao@marvell.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b8e6c91c
...@@ -170,13 +170,41 @@ config MACH_E800 ...@@ -170,13 +170,41 @@ config MACH_E800
Say Y here if you intend to run this kernel on a Toshiba Say Y here if you intend to run this kernel on a Toshiba
e800 family PDA. e800 family PDA.
config TRIZEPS_PXA
bool "PXA based Keith und Koep Trizeps DIMM-Modules"
config MACH_TRIZEPS4 config MACH_TRIZEPS4
bool "Keith und Koep Trizeps4 DIMM-Module" bool "Keith und Koep Trizeps4 DIMM-Module"
depends on TRIZEPS_PXA
select TRIZEPS_PCMCIA
select PXA27x
config MACH_TRIZEPS4WL
bool "Keith und Koep Trizeps4-WL DIMM-Module"
depends on TRIZEPS_PXA
select TRIZEPS_PCMCIA
select PXA27x select PXA27x
select PXA_SSP
config MACH_TRIZEPS4_CONXS choice
prompt "Select base board for Trizeps module"
depends on TRIZEPS_PXA
config MACH_TRIZEPS_CONXS
bool "ConXS Eval Board" bool "ConXS Eval Board"
depends on MACH_TRIZEPS4
config MACH_TRIZEPS_UCONXS
bool "uConXS Eval Board"
config MACH_TRIZEPS_ANY
bool "another Board"
endchoice
config TRIZEPS_PCMCIA
bool
help
Enable PCMCIA support for Trizeps modules
config MACH_EM_X270 config MACH_EM_X270
bool "CompuLab EM-x270 platform" bool "CompuLab EM-x270 platform"
......
...@@ -17,11 +17,16 @@ ...@@ -17,11 +17,16 @@
#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ #define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */
#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ #define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board CSFR register */ /* Logic on ConXS-board CSFR register*/
#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic chip on ConXS-Board BOCR register */ #define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS)
#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic chip on ConXS-Board IRCR register*/ /* Logic on ConXS-board BOCR register*/
#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic chip on ConXS-Board UPSR register*/ #define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000)
#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* Logic chip on ConXS-Board DICR register*/ /* Logic on ConXS-board IRCR register*/
#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000)
/* Logic on ConXS-board UPSR register*/
#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000)
/* Logic on ConXS-board DICR register*/
#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000)
/* virtual memory regions */ /* virtual memory regions */
#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ #define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
...@@ -54,6 +59,15 @@ ...@@ -54,6 +59,15 @@
#define GPIO_MMC_DET 12 #define GPIO_MMC_DET 12
#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET) #define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET)
/* DOC NAND chip */
#define GPIO_DOC_LOCK 94
#define GPIO_DOC_IRQ 93
#define TRIZEPS4_DOC_IRQ IRQ_GPIO(GPIO_DOC_IRQ)
/* SPI interface */
#define GPIO_SPI 53
#define TRIZEPS4_SPI_IRQ IRQ_GPIO(GPIO_SPI)
/* LEDS using tx2 / rx2 */ /* LEDS using tx2 / rx2 */
#define GPIO_SYS_BUSY_LED 46 #define GPIO_SYS_BUSY_LED 46
#define GPIO_HEARTBEAT_LED 47 #define GPIO_HEARTBEAT_LED 47
...@@ -62,24 +76,66 @@ ...@@ -62,24 +76,66 @@
#define GPIO_PIC 0 #define GPIO_PIC 0
#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC) #define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC)
#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) #ifdef CONFIG_MACH_TRIZEPS_CONXS
#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) /* for CONXS base board define these registers */
#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) #define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) #define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) #define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) #define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
#define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT)
#define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#define ConXS_CFSR (*((volatile unsigned short *)CFSR_P2V(0x0C000000))) static inline unsigned short CFSR_readw(void)
#define ConXS_BCR (*((volatile unsigned short *)BCR_P2V(0x0E000000))) {
#define ConXS_DCR (*((volatile unsigned short *)DCR_P2V(0x0F800000))) /* [Compact Flash Status Register] is read only */
return *((unsigned short *)CFSR_P2V(0x0C000000));
}
static inline void BCR_writew(unsigned short value)
{
/* [Board Control Regsiter] is write only */
*((unsigned short *)BCR_P2V(0x0E000000)) = value;
}
static inline void DCR_writew(unsigned short value)
{
/* [Display Control Register] is write only */
*((unsigned short *)DCR_P2V(0x0E000000)) = value;
}
static inline void IRCR_writew(unsigned short value)
{
/* [InfraRed data Control Register] is write only */
*((unsigned short *)IRCR_P2V(0x0E000000)) = value;
}
#else #else
#define ConXS_CFSR CFSR_P2V(0x0C000000) #define ConXS_CFSR CFSR_P2V(0x0C000000)
#define ConXS_BCR BCR_P2V(0x0E000000) #define ConXS_BCR BCR_P2V(0x0E000000)
#define ConXS_DCR DCR_P2V(0x0F800000) #define ConXS_DCR DCR_P2V(0x0F800000)
#define ConXS_IRCR IRCR_P2V(0x0F800000)
#endif #endif
#else
/* for whatever baseboard define function registers */
static inline unsigned short CFSR_readw(void)
{
return 0;
}
static inline void BCR_writew(unsigned short value)
{
;
}
static inline void DCR_writew(unsigned short value)
{
;
}
static inline void IRCR_writew(unsigned short value)
{
;
}
#endif /* CONFIG_MACH_TRIZEPS_CONXS */
#define ConXS_CFSR_BVD_MASK 0x0003 #define ConXS_CFSR_BVD_MASK 0x0003
#define ConXS_CFSR_BVD1 (1 << 0) #define ConXS_CFSR_BVD1 (1 << 0)
......
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