[ARM PATCH] 2307/1: Add IXP46x and IXDPG465 implementation

Patch from Deepak Saxena

Patch adds implementation details for IXP46x CPUs and new IXDPG465
reference platform. 

Signed-off-by: Deepak Saxena
Signed-off-by: Russell King

arch/arm/mach-ixp4xx/Kconfig

@@ -36,6 +36,14 @@ config MACH_IXDPG425
 	  IXDPG425 Development Platform (Also known as Montajade).
 	  For more information on this platform, see Documentation/arm/IXP4xx.
 
+config MACH_IXDP465
+	bool "IXDP465"
+	help
+	  Say 'Y' here if you want your kernel to support Intel's
+	  IXDP465 Development Platform (Also known as BMP).
+	  For more information on this platform, see Documentation/arm/IXP4xx.
+
+
 #
 # IXCDP1100 is the exact same HW as IXDP425, but with a different machine 
 # number from the bootloader due to marketing monkeys, so we just enable it 
@@ -58,7 +66,15 @@ config ARCH_PRPMC1100
 #
 config	ARCH_IXDP4XX
 	bool
-	depends on ARCH_IXDP425 || ARCH_AVILA
+	depends on ARCH_IXDP425 || ARCH_AVILA || MACH_IXDP465
+	default y
+
+#
+# Certain registers and IRQs are only enabled if supporting IXP465 CPUs
+#
+config CPU_IXP46X
+	bool
+	depends on MACH_IXDP465
 	default y
 
 comment "IXP4xx Options"

arch/arm/mach-ixp4xx/common-pci.c

@@ -348,10 +348,11 @@ void __init ixp4xx_pci_preinit(void)
 	asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
 
 	/*
-	 * Determine which PCI read method to use
+	 * Determine which PCI read method to use.
+	 * Rev 0 IXP425 requires workaround.
 	 */
-	if (!(processor_id & 0xf)) {
-		printk("PCI: IXP4xx A0 silicon detected - "
+	if (!(processor_id & 0xf) && !cpu_is_ixp46x()) {
+		printk("PCI: IXP42x A0 silicon detected - "
 			"PCI Non-Prefetch Workaround Enabled\n");
 		ixp4xx_pci_read = ixp4xx_pci_read_errata;
 	} else

arch/arm/mach-ixp4xx/common.c

@@ -145,7 +145,10 @@ void __init ixp4xx_map_io(void)
  **************************************************************************/
 static void ixp4xx_irq_mask(unsigned int irq)
 {
-	*IXP4XX_ICMR &= ~(1 << irq);
+	if (cpu_is_ixp46x() && irq >= 32)
+		*IXP4XX_ICMR2 &= ~(1 << (irq - 32));
+	else
+		*IXP4XX_ICMR &= ~(1 << irq);
 }
 
 static void ixp4xx_irq_mask_ack(unsigned int irq)
@@ -155,13 +158,13 @@ static void ixp4xx_irq_mask_ack(unsigned int irq)
 
 static void ixp4xx_irq_unmask(unsigned int irq)
 {
-	static int irq2gpio[NR_IRQS] = {
+	static int irq2gpio[32] = {
 		-1, -1, -1, -1, -1, -1,  0,  1,
 		-1, -1, -1, -1, -1, -1, -1, -1,
 		-1, -1, -1,  2,  3,  4,  5,  6,
 		 7,  8,  9, 10, 11, 12, -1, -1,
 	};
-	int line = irq2gpio[irq];
+	int line = (irq < 32) ? irq2gpio[irq] : -1;
 
 	/*
 	 * This only works for LEVEL gpio IRQs as per the IXP4xx developer's
@@ -171,7 +174,10 @@ static void ixp4xx_irq_unmask(unsigned int irq)
 	if (line >= 0)
 		gpio_line_isr_clear(line);
 
-	*IXP4XX_ICMR |= (1 << irq);
+	if (cpu_is_ixp46x() && irq >= 32)
+		*IXP4XX_ICMR2 |= (1 << (irq - 32));
+	else
+		*IXP4XX_ICMR |= (1 << irq);
 }
 
 static struct irqchip ixp4xx_irq_chip = {
@@ -190,6 +196,14 @@ void __init ixp4xx_init_irq(void)
 	/* Disable all interrupt */
 	*IXP4XX_ICMR = 0x0; 
 
+	if (cpu_is_ixp46x()) {
+		/* Route upper 32 sources to IRQ instead of FIQ */
+		*IXP4XX_ICLR2 = 0x00;
+
+		/* Disable upper 32 interrupts */
+		*IXP4XX_ICMR2 = 0x00;
+	}
+
 	for(i = 0; i < NR_IRQS; i++)
 	{
 		set_irq_chip(i, &ixp4xx_irq_chip);

arch/arm/mach-ixp4xx/ixdp425-pci.c

@@ -73,9 +73,8 @@ struct hw_pci ixdp425_pci __initdata = {
 
 int __init ixdp425_pci_init(void)
 {
-	if (machine_is_ixdp425() || 
-		machine_is_ixcdp1100() || 
-		machine_is_avila())
+	if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
+			machine_is_avila() || machine_is_ixdp465())
 		pci_common_init(&ixdp425_pci);
 	return 0;
 }

arch/arm/mach-ixp4xx/ixdp425-setup.c

@@ -108,6 +108,13 @@ static struct platform_device *ixdp425_devices[] __initdata = {
 
 static void __init ixdp425_init(void)
 {
+	/*
+	 * IXP465 has 32MB window
+	 */
+	if (machine_is_ixdp465()) {
+		ixdp425_flash_resource.end += IXDP425_FLASH_SIZE;
+	}
+
 	platform_add_devices(&ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
 }
 
@@ -122,6 +129,17 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
 	INIT_MACHINE(ixdp425_init)
 MACHINE_END
 
+MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
+	MAINTAINER("MontaVista Software, Inc.")
+	BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
+		IXP4XX_PERIPHERAL_BASE_VIRT)
+	MAPIO(ixdp425_map_io)
+	INITIRQ(ixp4xx_init_irq)
+	.timer		= &ixp4xx_timer,
+	BOOT_PARAMS(0x0100)
+	INIT_MACHINE(ixdp425_init)
+MACHINE_END
+
 MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
 	MAINTAINER("MontaVista Software, Inc.")
 	BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,