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Commit 645a7fe1 authored by David S. Miller's avatar David S. Miller
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Merge branch 'ksz886x-cable-test' 

Oleksij Rempel says:

====================
provide cable test support for the ksz886x switch

changes v5:
- drop resume() patch
- add Reviewed-by tags.
- rework dsa_slave_phy_connect() patch

changes v4:
- use fallthrough;
- use EOPNOTSUPP instead of ENOTSUPP
- drop flags variable in dsa_slave_phy_connect patch
- extend description for the "net: phy: micrel: apply resume errat"
  patch
- fix "use consistent alignments" patch

changes v3:
- remove RFC tag

changes v2:
- use generic MII_* defines where possible
- rework phylink validate
- remove phylink get state function
- reorder cabletest patches to make PHY flag patch in the right order
- fix MDI-X detection

This patches provide support for cable testing on the ksz886x switches.
Since it has one special port, we needed to add phylink with validation
and extra quirk for the PHY to signal, that one port will not provide
valid cable testing reports.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents ffa85b73 49011e0c
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Showing with 573 additions and 237 deletions
drivers/net/dsa/microchip/ksz8795.c
View file @ 645a7fe1
This diff is collapsed.
drivers/net/dsa/microchip/ksz8795_reg.h
View file @ 645a7fe1
......@@ -249,7 +249,7 @@
#define REG_PORT_4_LINK_MD_CTRL 0x4A
#define PORT_CABLE_10M_SHORT BIT(7)
#define PORT_CABLE_DIAG_RESULT_M 0x3
#define PORT_CABLE_DIAG_RESULT_M GENMASK(6, 5)
#define PORT_CABLE_DIAG_RESULT_S 5
#define PORT_CABLE_STAT_NORMAL 0
#define PORT_CABLE_STAT_OPEN 1
......@@ -744,68 +744,6 @@
#define PORT_ACL_FORCE_DLR_MISS BIT(0)
#ifndef PHY_REG_CTRL
#define PHY_REG_CTRL 0
#define PHY_RESET BIT(15)
#define PHY_LOOPBACK BIT(14)
#define PHY_SPEED_100MBIT BIT(13)
#define PHY_AUTO_NEG_ENABLE BIT(12)
#define PHY_POWER_DOWN BIT(11)
#define PHY_MII_DISABLE BIT(10)
#define PHY_AUTO_NEG_RESTART BIT(9)
#define PHY_FULL_DUPLEX BIT(8)
#define PHY_COLLISION_TEST_NOT BIT(7)
#define PHY_HP_MDIX BIT(5)
#define PHY_FORCE_MDIX BIT(4)
#define PHY_AUTO_MDIX_DISABLE BIT(3)
#define PHY_REMOTE_FAULT_DISABLE BIT(2)
#define PHY_TRANSMIT_DISABLE BIT(1)
#define PHY_LED_DISABLE BIT(0)
#define PHY_REG_STATUS 1
#define PHY_100BT4_CAPABLE BIT(15)
#define PHY_100BTX_FD_CAPABLE BIT(14)
#define PHY_100BTX_CAPABLE BIT(13)
#define PHY_10BT_FD_CAPABLE BIT(12)
#define PHY_10BT_CAPABLE BIT(11)
#define PHY_MII_SUPPRESS_CAPABLE_NOT BIT(6)
#define PHY_AUTO_NEG_ACKNOWLEDGE BIT(5)
#define PHY_REMOTE_FAULT BIT(4)
#define PHY_AUTO_NEG_CAPABLE BIT(3)
#define PHY_LINK_STATUS BIT(2)
#define PHY_JABBER_DETECT_NOT BIT(1)
#define PHY_EXTENDED_CAPABILITY BIT(0)
#define PHY_REG_ID_1 2
#define PHY_REG_ID_2 3
#define PHY_REG_AUTO_NEGOTIATION 4
#define PHY_AUTO_NEG_NEXT_PAGE_NOT BIT(15)
#define PHY_AUTO_NEG_REMOTE_FAULT_NOT BIT(13)
#define PHY_AUTO_NEG_SYM_PAUSE BIT(10)
#define PHY_AUTO_NEG_100BT4 BIT(9)
#define PHY_AUTO_NEG_100BTX_FD BIT(8)
#define PHY_AUTO_NEG_100BTX BIT(7)
#define PHY_AUTO_NEG_10BT_FD BIT(6)
#define PHY_AUTO_NEG_10BT BIT(5)
#define PHY_AUTO_NEG_SELECTOR 0x001F
#define PHY_AUTO_NEG_802_3 0x0001
#define PHY_REG_REMOTE_CAPABILITY 5
#define PHY_REMOTE_NEXT_PAGE_NOT BIT(15)
#define PHY_REMOTE_ACKNOWLEDGE_NOT BIT(14)
#define PHY_REMOTE_REMOTE_FAULT_NOT BIT(13)
#define PHY_REMOTE_SYM_PAUSE BIT(10)
#define PHY_REMOTE_100BTX_FD BIT(8)
#define PHY_REMOTE_100BTX BIT(7)
#define PHY_REMOTE_10BT_FD BIT(6)
#define PHY_REMOTE_10BT BIT(5)
#endif
#define KSZ8795_ID_HI 0x0022
#define KSZ8795_ID_LO 0x1550
#define KSZ8863_ID_LO 0x1430
......@@ -815,13 +753,14 @@
#define PHY_REG_LINK_MD 0x1D
#define PHY_START_CABLE_DIAG BIT(15)
#define PHY_CABLE_DIAG_RESULT_M GENMASK(14, 13)
#define PHY_CABLE_DIAG_RESULT 0x6000
#define PHY_CABLE_STAT_NORMAL 0x0000
#define PHY_CABLE_STAT_OPEN 0x2000
#define PHY_CABLE_STAT_SHORT 0x4000
#define PHY_CABLE_STAT_FAILED 0x6000
#define PHY_CABLE_10M_SHORT BIT(12)
#define PHY_CABLE_FAULT_COUNTER 0x01FF
#define PHY_CABLE_FAULT_COUNTER_M GENMASK(8, 0)
#define PHY_REG_PHY_CTRL 0x1F
......
drivers/net/ethernet/micrel/ksz884x.c
View file @ 645a7fe1
......@@ -25,6 +25,7 @@
#include <linux/crc32.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/micrel_phy.h>
/* DMA Registers */
......@@ -271,84 +272,15 @@
#define KS884X_PHY_CTRL_OFFSET 0x00
/* Mode Control Register */
#define PHY_REG_CTRL 0
#define PHY_RESET 0x8000
#define PHY_LOOPBACK 0x4000
#define PHY_SPEED_100MBIT 0x2000
#define PHY_AUTO_NEG_ENABLE 0x1000
#define PHY_POWER_DOWN 0x0800
#define PHY_MII_DISABLE 0x0400
#define PHY_AUTO_NEG_RESTART 0x0200
#define PHY_FULL_DUPLEX 0x0100
#define PHY_COLLISION_TEST 0x0080
#define PHY_HP_MDIX 0x0020
#define PHY_FORCE_MDIX 0x0010
#define PHY_AUTO_MDIX_DISABLE 0x0008
#define PHY_REMOTE_FAULT_DISABLE 0x0004
#define PHY_TRANSMIT_DISABLE 0x0002
#define PHY_LED_DISABLE 0x0001
#define KS884X_PHY_STATUS_OFFSET 0x02
/* Mode Status Register */
#define PHY_REG_STATUS 1
#define PHY_100BT4_CAPABLE 0x8000
#define PHY_100BTX_FD_CAPABLE 0x4000
#define PHY_100BTX_CAPABLE 0x2000
#define PHY_10BT_FD_CAPABLE 0x1000
#define PHY_10BT_CAPABLE 0x0800
#define PHY_MII_SUPPRESS_CAPABLE 0x0040
#define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020
#define PHY_REMOTE_FAULT 0x0010
#define PHY_AUTO_NEG_CAPABLE 0x0008
#define PHY_LINK_STATUS 0x0004
#define PHY_JABBER_DETECT 0x0002
#define PHY_EXTENDED_CAPABILITY 0x0001
#define KS884X_PHY_ID_1_OFFSET 0x04
#define KS884X_PHY_ID_2_OFFSET 0x06
/* PHY Identifier Registers */
#define PHY_REG_ID_1 2
#define PHY_REG_ID_2 3
#define KS884X_PHY_AUTO_NEG_OFFSET 0x08
/* Auto-Negotiation Advertisement Register */
#define PHY_REG_AUTO_NEGOTIATION 4
#define PHY_AUTO_NEG_NEXT_PAGE 0x8000
#define PHY_AUTO_NEG_REMOTE_FAULT 0x2000
/* Not supported. */
#define PHY_AUTO_NEG_ASYM_PAUSE 0x0800
#define PHY_AUTO_NEG_SYM_PAUSE 0x0400
#define PHY_AUTO_NEG_100BT4 0x0200
#define PHY_AUTO_NEG_100BTX_FD 0x0100
#define PHY_AUTO_NEG_100BTX 0x0080
#define PHY_AUTO_NEG_10BT_FD 0x0040
#define PHY_AUTO_NEG_10BT 0x0020
#define PHY_AUTO_NEG_SELECTOR 0x001F
#define PHY_AUTO_NEG_802_3 0x0001
#define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE)
#define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
/* Auto-Negotiation Link Partner Ability Register */
#define PHY_REG_REMOTE_CAPABILITY 5
#define PHY_REMOTE_NEXT_PAGE 0x8000
#define PHY_REMOTE_ACKNOWLEDGE 0x4000
#define PHY_REMOTE_REMOTE_FAULT 0x2000
#define PHY_REMOTE_SYM_PAUSE 0x0400
#define PHY_REMOTE_100BTX_FD 0x0100
#define PHY_REMOTE_100BTX 0x0080
#define PHY_REMOTE_10BT_FD 0x0040
#define PHY_REMOTE_10BT 0x0020
/* P1VCT */
#define KS884X_P1VCT_P 0x04F0
#define KS884X_P1PHYCTRL_P 0x04F2
......@@ -2886,15 +2818,6 @@ static void sw_block_addr(struct ksz_hw *hw)
}
}
#define PHY_LINK_SUPPORT \
(PHY_AUTO_NEG_ASYM_PAUSE | \
PHY_AUTO_NEG_SYM_PAUSE | \
PHY_AUTO_NEG_100BT4 | \
PHY_AUTO_NEG_100BTX_FD | \
PHY_AUTO_NEG_100BTX | \
PHY_AUTO_NEG_10BT_FD | \
PHY_AUTO_NEG_10BT)
static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
{
*data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
......@@ -3238,16 +3161,18 @@ static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
rx = tx = 0;
if (port->force_link)
rx = tx = 1;
if (remote & PHY_AUTO_NEG_SYM_PAUSE) {
if (local & PHY_AUTO_NEG_SYM_PAUSE) {
if (remote & LPA_PAUSE_CAP) {
if (local & ADVERTISE_PAUSE_CAP) {
rx = tx = 1;
} else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) &&
(local & PHY_AUTO_NEG_PAUSE) ==
PHY_AUTO_NEG_ASYM_PAUSE) {
} else if ((remote & LPA_PAUSE_ASYM) &&
(local &
(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) ==
ADVERTISE_PAUSE_ASYM) {
tx = 1;
}
} else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) {
if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE)
} else if (remote & LPA_PAUSE_ASYM) {
if ((local & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM))
== (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM))
rx = 1;
}
if (!hw->ksz_switch)
......@@ -3428,16 +3353,16 @@ static void port_force_link_speed(struct ksz_port *port)
phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
hw_r_phy_ctrl(hw, phy, &data);
data &= ~PHY_AUTO_NEG_ENABLE;
data &= ~BMCR_ANENABLE;
if (10 == port->speed)
data &= ~PHY_SPEED_100MBIT;
data &= ~BMCR_SPEED100;
else if (100 == port->speed)
data |= PHY_SPEED_100MBIT;
data |= BMCR_SPEED100;
if (1 == port->duplex)
data &= ~PHY_FULL_DUPLEX;
data &= ~BMCR_FULLDPLX;
else if (2 == port->duplex)
data |= PHY_FULL_DUPLEX;
data |= BMCR_FULLDPLX;
hw_w_phy_ctrl(hw, phy, data);
}
}
......
drivers/net/phy/micrel.c
View file @ 645a7fe1
This diff is collapsed.
include/linux/micrel_phy.h
View file @ 645a7fe1
......@@ -39,10 +39,26 @@
/* struct phy_device dev_flags definitions */
#define MICREL_PHY_50MHZ_CLK 0x00000001
#define MICREL_PHY_FXEN 0x00000002
#define MICREL_KSZ8_P1_ERRATA 0x00000003
#define MICREL_KSZ9021_EXTREG_CTRL 0xB
#define MICREL_KSZ9021_EXTREG_DATA_WRITE 0xC
#define MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW 0x104
#define MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW 0x105
/* Device specific MII_BMCR (Reg 0) bits */
/* 1 = HP Auto MDI/MDI-X mode, 0 = Microchip Auto MDI/MDI-X mode */
#define KSZ886X_BMCR_HP_MDIX BIT(5)
/* 1 = Force MDI (transmit on RXP/RXM pins), 0 = Normal operation
* (transmit on TXP/TXM pins)
*/
#define KSZ886X_BMCR_FORCE_MDI BIT(4)
/* 1 = Disable auto MDI-X */
#define KSZ886X_BMCR_DISABLE_AUTO_MDIX BIT(3)
#define KSZ886X_BMCR_DISABLE_FAR_END_FAULT BIT(2)
#define KSZ886X_BMCR_DISABLE_TRANSMIT BIT(1)
#define KSZ886X_BMCR_DISABLE_LED BIT(0)
#define KSZ886X_CTRL_MDIX_STAT BIT(4)
#endif /* _MICREL_PHY_H */
net/dsa/slave.c
View file @ 645a7fe1
......@@ -1749,7 +1749,8 @@ static void dsa_slave_phylink_fixed_state(struct phylink_config *config,
}
/* slave device setup *******************************************************/
static int dsa_slave_phy_connect(struct net_device *slave_dev, int addr)
static int dsa_slave_phy_connect(struct net_device *slave_dev, int addr,
u32 flags)
{
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
struct dsa_switch *ds = dp->ds;
......@@ -1760,6 +1761,8 @@ static int dsa_slave_phy_connect(struct net_device *slave_dev, int addr)
return -ENODEV;
}
slave_dev->phydev->dev_flags |= flags;
return phylink_connect_phy(dp->pl, slave_dev->phydev);
}
......@@ -1804,7 +1807,7 @@ static int dsa_slave_phy_setup(struct net_device *slave_dev)
/* We could not connect to a designated PHY or SFP, so try to
* use the switch internal MDIO bus instead
*/
ret = dsa_slave_phy_connect(slave_dev, dp->index);
ret = dsa_slave_phy_connect(slave_dev, dp->index, phy_flags);
if (ret) {
netdev_err(slave_dev,
"failed to connect to port %d: %d\n",
......
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