Commit 6495892c authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Greg Kroah-Hartman

coresight tmc: Add support for Coresight SoC 600 TMC

The coresight SoC 600 supports ETR save-restore which allows us
to restore a trace session by retaining the RRP/RWP/STS.Full values
when the TMC leaves the Disabled state. However, the TMC doesn't
have a scatter-gather unit in built.

Also, TMCs have different PIDs in different configurations (ETF,
ETB & ETR), unlike the previous generation.

While the DEVID exposes some of the features/changes in the TMC,
it doesn't explicitly advertises the new save-restore feature
as described above.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f2e931a2
...@@ -442,6 +442,22 @@ static struct amba_id tmc_ids[] = { ...@@ -442,6 +442,22 @@ static struct amba_id tmc_ids[] = {
.id = 0x0003b961, .id = 0x0003b961,
.mask = 0x0003ffff, .mask = 0x0003ffff,
}, },
{
/* Coresight SoC 600 TMC-ETR/ETS */
.id = 0x000bb9e8,
.mask = 0x000fffff,
.data = (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS,
},
{
/* Coresight SoC 600 TMC-ETB */
.id = 0x000bb9e9,
.mask = 0x000fffff,
},
{
/* Coresight SoC 600 TMC-ETF */
.id = 0x000bb9ea,
.mask = 0x000fffff,
},
{ 0, 0}, { 0, 0},
}; };
......
...@@ -129,6 +129,10 @@ enum tmc_mem_intf_width { ...@@ -129,6 +129,10 @@ enum tmc_mem_intf_width {
*/ */
#define TMC_ETR_SAVE_RESTORE (0x1U << 2) #define TMC_ETR_SAVE_RESTORE (0x1U << 2)
/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
#define CORESIGHT_SOC_600_ETR_CAPS \
(TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
/** /**
* struct tmc_drvdata - specifics associated to an TMC component * struct tmc_drvdata - specifics associated to an TMC component
* @base: memory mapped base address for this component. * @base: memory mapped base address for this component.
......
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