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Commit 64c672ae authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/pwr: implement a simple i2c stack 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 2e9dfe23
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Showing with 2066 additions and 279 deletions
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc 0 → 100644
View file @ 64c672ae
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#define T_TIMEOUT 2200000
#define T_RISEFALL 1000
#define T_HOLD 5000
#ifdef INCLUDE_PROC
process(PROC_I2C_, #i2c_init, #i2c_recv)
#endif
/******************************************************************************
* I2C_ data segment
*****************************************************************************/
#ifdef INCLUDE_DATA
i2c_scl_map:
.b32 NV_PPWR_OUTPUT_I2C_0_SCL
.b32 NV_PPWR_OUTPUT_I2C_1_SCL
.b32 NV_PPWR_OUTPUT_I2C_2_SCL
.b32 NV_PPWR_OUTPUT_I2C_3_SCL
.b32 NV_PPWR_OUTPUT_I2C_4_SCL
.b32 NV_PPWR_OUTPUT_I2C_5_SCL
.b32 NV_PPWR_OUTPUT_I2C_6_SCL
.b32 NV_PPWR_OUTPUT_I2C_7_SCL
.b32 NV_PPWR_OUTPUT_I2C_8_SCL
.b32 NV_PPWR_OUTPUT_I2C_9_SCL
i2c_sda_map:
.b32 NV_PPWR_OUTPUT_I2C_0_SDA
.b32 NV_PPWR_OUTPUT_I2C_1_SDA
.b32 NV_PPWR_OUTPUT_I2C_2_SDA
.b32 NV_PPWR_OUTPUT_I2C_3_SDA
.b32 NV_PPWR_OUTPUT_I2C_4_SDA
.b32 NV_PPWR_OUTPUT_I2C_5_SDA
.b32 NV_PPWR_OUTPUT_I2C_6_SDA
.b32 NV_PPWR_OUTPUT_I2C_7_SDA
.b32 NV_PPWR_OUTPUT_I2C_8_SDA
.b32 NV_PPWR_OUTPUT_I2C_9_SDA
#if NVKM_PPWR_CHIPSET < GF119
i2c_ctrl:
.b32 0x00e138
.b32 0x00e150
.b32 0x00e168
.b32 0x00e180
.b32 0x00e254
.b32 0x00e274
.b32 0x00e764
.b32 0x00e780
.b32 0x00e79c
.b32 0x00e7b8
#endif
#endif
/******************************************************************************
* I2C_ code segment
*****************************************************************************/
#ifdef INCLUDE_CODE
// $r3 - value
// $r2 - sda line
// $r1 - scl line
// $r0 - zero
i2c_drive_scl:
cmp b32 $r3 0
bra e #i2c_drive_scl_lo
nv_iowr(NV_PPWR_OUTPUT_SET, $r1)
ret
i2c_drive_scl_lo:
nv_iowr(NV_PPWR_OUTPUT_CLR, $r1)
ret
i2c_drive_sda:
cmp b32 $r3 0
bra e #i2c_drive_sda_lo
nv_iowr(NV_PPWR_OUTPUT_SET, $r2)
ret
i2c_drive_sda_lo:
nv_iowr(NV_PPWR_OUTPUT_CLR, $r2)
ret
i2c_sense_scl:
bclr $flags $p1
nv_iord($r3, NV_PPWR_INPUT)
and $r3 $r1
bra z #i2c_sense_scl_done
bset $flags $p1
i2c_sense_scl_done:
ret
i2c_sense_sda:
bclr $flags $p1
nv_iord($r3, NV_PPWR_INPUT)
and $r3 $r2
bra z #i2c_sense_sda_done
bset $flags $p1
i2c_sense_sda_done:
ret
#define i2c_drive_scl(v) /*
*/ mov $r3 (v) /*
*/ call(i2c_drive_scl)
#define i2c_drive_sda(v) /*
*/ mov $r3 (v) /*
*/ call(i2c_drive_sda)
#define i2c_sense_scl() /*
*/ call(i2c_sense_scl)
#define i2c_sense_sda() /*
*/ call(i2c_sense_sda)
#define i2c_delay(v) /*
*/ mov $r14 (v) /*
*/ call(nsec)
#define i2c_trace_init() /*
*/ imm32($r6, 0x10000000) /*
*/ sub b32 $r7 $r6 1 /*
*/
#define i2c_trace_down() /*
*/ shr b32 $r6 4 /*
*/ push $r5 /*
*/ shl b32 $r5 $r6 4 /*
*/ sub b32 $r5 $r6 /*
*/ not b32 $r5 /*
*/ and $r7 $r5 /*
*/ pop $r5 /*
*/
#define i2c_trace_exit() /*
*/ shl b32 $r6 4 /*
*/
#define i2c_trace_next() /*
*/ add b32 $r7 $r6 /*
*/
#define i2c_trace_call(func) /*
*/ i2c_trace_next() /*
*/ i2c_trace_down() /*
*/ call(func) /*
*/ i2c_trace_exit() /*
*/
i2c_raise_scl:
push $r4
mov $r4 (T_TIMEOUT / T_RISEFALL)
i2c_drive_scl(1)
i2c_raise_scl_wait:
i2c_delay(T_RISEFALL)
i2c_sense_scl()
bra $p1 #i2c_raise_scl_done
sub b32 $r4 1
bra nz #i2c_raise_scl_wait
i2c_raise_scl_done:
pop $r4
ret
i2c_start:
i2c_sense_scl()
bra not $p1 #i2c_start_rep
i2c_sense_sda()
bra not $p1 #i2c_start_rep
bra #i2c_start_send
i2c_start_rep:
i2c_drive_scl(0)
i2c_drive_sda(1)
i2c_trace_call(i2c_raise_scl)
bra not $p1 #i2c_start_out
i2c_start_send:
i2c_drive_sda(0)
i2c_delay(T_HOLD)
i2c_drive_scl(0)
i2c_delay(T_HOLD)
i2c_start_out:
ret
i2c_stop:
i2c_drive_scl(0)
i2c_drive_sda(0)
i2c_delay(T_RISEFALL)
i2c_drive_scl(1)
i2c_delay(T_HOLD)
i2c_drive_sda(1)
i2c_delay(T_HOLD)
ret
// $r3 - value
// $r2 - sda line
// $r1 - scl line
// $r0 - zero
i2c_bitw:
call(i2c_drive_sda)
i2c_delay(T_RISEFALL)
i2c_trace_call(i2c_raise_scl)
bra not $p1 #i2c_bitw_out
i2c_delay(T_HOLD)
i2c_drive_scl(0)
i2c_delay(T_HOLD)
i2c_bitw_out:
ret
// $r3 - value (out)
// $r2 - sda line
// $r1 - scl line
// $r0 - zero
i2c_bitr:
i2c_drive_sda(1)
i2c_delay(T_RISEFALL)
i2c_trace_call(i2c_raise_scl)
bra not $p1 #i2c_bitr_done
i2c_sense_sda()
i2c_drive_scl(0)
i2c_delay(T_HOLD)
xbit $r3 $flags $p1
bset $flags $p1
i2c_bitr_done:
ret
i2c_get_byte:
mov $r5 0
mov $r4 8
i2c_get_byte_next:
shl b32 $r5 1
i2c_trace_call(i2c_bitr)
bra not $p1 #i2c_get_byte_done
or $r5 $r3
sub b32 $r4 1
bra nz #i2c_get_byte_next
mov $r3 1
i2c_trace_call(i2c_bitw)
i2c_get_byte_done:
ret
i2c_put_byte:
mov $r4 8
i2c_put_byte_next:
sub b32 $r4 1
xbit $r3 $r5 $r4
i2c_trace_call(i2c_bitw)
bra not $p1 #i2c_put_byte_done
cmp b32 $r4 0
bra ne #i2c_put_byte_next
i2c_trace_call(i2c_bitr)
bra not $p1 #i2c_put_byte_done
i2c_trace_next()
cmp b32 $r3 1
bra ne #i2c_put_byte_done
bclr $flags $p1 // nack
i2c_put_byte_done:
ret
i2c_addr:
i2c_trace_call(i2c_start)
bra not $p1 #i2c_addr_done
extr $r3 $r12 I2C__MSG_DATA0_ADDR
shl b32 $r3 1
or $r5 $r3
i2c_trace_call(i2c_put_byte)
i2c_addr_done:
ret
i2c_acquire_addr:
extr $r14 $r12 I2C__MSG_DATA0_PORT
#if NVKM_PPWR_CHIPSET < GF119
shl b32 $r14 2
add b32 $r14 #i2c_ctrl
ld b32 $r14 D[$r14]
#else
shl b32 $r14 5
add b32 $r14 0x00d014
#endif
ret
i2c_acquire:
call(i2c_acquire_addr)
call(rd32)
bset $r13 3
call(wr32)
ret
i2c_release:
call(i2c_acquire_addr)
call(rd32)
bclr $r13 3
call(wr32)
ret
// description
//
// $r15 - current (i2c)
// $r14 - sender process name
// $r13 - message
// $r12 - data0
// $r11 - data1
// $r0 - zero
i2c_recv:
bclr $flags $p1
extr $r1 $r12 I2C__MSG_DATA0_PORT
shl b32 $r1 2
cmp b32 $r1 (#i2c_sda_map - #i2c_scl_map)
bra ge #i2c_recv_done
add b32 $r3 $r1 #i2c_sda_map
ld b32 $r2 D[$r3]
add b32 $r3 $r1 #i2c_scl_map
ld b32 $r1 D[$r3]
bset $flags $p2
push $r13
push $r14
push $r13
i2c_trace_init()
i2c_trace_call(i2c_acquire)
pop $r13
cmp b32 $r13 I2C__MSG_RD08
bra ne #i2c_recv_not_rd08
mov $r5 0
i2c_trace_call(i2c_addr)
bra not $p1 #i2c_recv_done
extr $r5 $r12 I2C__MSG_DATA0_RD08_REG
i2c_trace_call(i2c_put_byte)
bra not $p1 #i2c_recv_done
mov $r5 1
i2c_trace_call(i2c_addr)
bra not $p1 #i2c_recv_done
i2c_trace_call(i2c_get_byte)
bra not $p1 #i2c_recv_done
ins $r11 $r5 I2C__MSG_DATA1_RD08_VAL
i2c_trace_call(i2c_stop)
mov b32 $r11 $r5
clear b32 $r7
bra #i2c_recv_done
i2c_recv_not_rd08:
cmp b32 $r13 I2C__MSG_WR08
bra ne #i2c_recv_not_wr08
mov $r5 0
call(i2c_addr)
bra not $p1 #i2c_recv_done
extr $r5 $r12 I2C__MSG_DATA0_WR08_REG
call(i2c_put_byte)
bra not $p1 #i2c_recv_done
mov $r5 0
call(i2c_addr)
bra not $p1 #i2c_recv_done
extr $r5 $r11 I2C__MSG_DATA1_WR08_VAL
call(i2c_put_byte)
bra not $p1 #i2c_recv_done
call(i2c_stop)
clear b32 $r7
extr $r5 $r12 I2C__MSG_DATA0_WR08_SYNC
bra nz #i2c_recv_done
bclr $flags $p2
bra #i2c_recv_done
i2c_recv_not_wr08:
i2c_recv_done:
extr $r14 $r12 I2C__MSG_DATA0_PORT
call(i2c_release)
pop $r14
pop $r13
bra not $p2 #i2c_recv_exit
mov b32 $r12 $r7
call(send)
i2c_recv_exit:
ret
// description
//
// $r15 - current (i2c)
// $r0 - zero
i2c_init:
ret
#endif
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
View file @ 64c672ae
......@@ -83,6 +83,50 @@
#define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002
#define NV_PPWR_OUTPUT 0x07c0
#define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004
#if NVKM_PPWR_CHIPSET < GF119
#define NV_PPWR_OUTPUT_I2C_3_SCL 0x00000100
#define NV_PPWR_OUTPUT_I2C_3_SDA 0x00000200
#define NV_PPWR_OUTPUT_I2C_0_SCL 0x00001000
#define NV_PPWR_OUTPUT_I2C_0_SDA 0x00002000
#define NV_PPWR_OUTPUT_I2C_1_SCL 0x00004000
#define NV_PPWR_OUTPUT_I2C_1_SDA 0x00008000
#define NV_PPWR_OUTPUT_I2C_2_SCL 0x00010000
#define NV_PPWR_OUTPUT_I2C_2_SDA 0x00020000
#define NV_PPWR_OUTPUT_I2C_4_SCL 0x00040000
#define NV_PPWR_OUTPUT_I2C_4_SDA 0x00080000
#define NV_PPWR_OUTPUT_I2C_5_SCL 0x00100000
#define NV_PPWR_OUTPUT_I2C_5_SDA 0x00200000
#define NV_PPWR_OUTPUT_I2C_6_SCL 0x00400000
#define NV_PPWR_OUTPUT_I2C_6_SDA 0x00800000
#define NV_PPWR_OUTPUT_I2C_7_SCL 0x01000000
#define NV_PPWR_OUTPUT_I2C_7_SDA 0x02000000
#define NV_PPWR_OUTPUT_I2C_8_SCL 0x04000000
#define NV_PPWR_OUTPUT_I2C_8_SDA 0x08000000
#define NV_PPWR_OUTPUT_I2C_9_SCL 0x10000000
#define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000
#else
#define NV_PPWR_OUTPUT_I2C_0_SCL 0x00000400
#define NV_PPWR_OUTPUT_I2C_1_SCL 0x00000800
#define NV_PPWR_OUTPUT_I2C_2_SCL 0x00001000
#define NV_PPWR_OUTPUT_I2C_3_SCL 0x00002000
#define NV_PPWR_OUTPUT_I2C_4_SCL 0x00004000
#define NV_PPWR_OUTPUT_I2C_5_SCL 0x00008000
#define NV_PPWR_OUTPUT_I2C_6_SCL 0x00010000
#define NV_PPWR_OUTPUT_I2C_7_SCL 0x00020000
#define NV_PPWR_OUTPUT_I2C_8_SCL 0x00040000
#define NV_PPWR_OUTPUT_I2C_9_SCL 0x00080000
#define NV_PPWR_OUTPUT_I2C_0_SDA 0x00100000
#define NV_PPWR_OUTPUT_I2C_1_SDA 0x00200000
#define NV_PPWR_OUTPUT_I2C_2_SDA 0x00400000
#define NV_PPWR_OUTPUT_I2C_3_SDA 0x00800000
#define NV_PPWR_OUTPUT_I2C_4_SDA 0x01000000
#define NV_PPWR_OUTPUT_I2C_5_SDA 0x02000000
#define NV_PPWR_OUTPUT_I2C_6_SDA 0x04000000
#define NV_PPWR_OUTPUT_I2C_7_SDA 0x08000000
#define NV_PPWR_OUTPUT_I2C_8_SDA 0x10000000
#define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000
#endif
#define NV_PPWR_INPUT 0x07c4
#define NV_PPWR_OUTPUT_SET 0x07e0
#define NV_PPWR_OUTPUT_SET_FB_PAUSE 0x00000004
#define NV_PPWR_OUTPUT_CLR 0x07e4
......@@ -125,6 +169,15 @@
*/ .b32 0 /*
*/ .skip 64
#if NV_PPWR_CHIPSET < GK208
#define imm32(reg,val) /*
*/ movw reg ((val) & 0x0000ffff) /*
*/ sethi reg ((val) & 0xffff0000)
#else
#define imm32(reg,val) /*
*/ mov reg (val)
#endif
#ifndef NVKM_FALCON_UNSHIFTED_IO
#define nv_iord(reg,ior) /*
*/ mov reg ior /*
......
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
View file @ 64c672ae
......@@ -37,6 +37,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_PROC
......@@ -46,6 +47,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_DATA
......@@ -57,6 +59,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_CODE
......
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
View file @ 64c672ae
......@@ -37,6 +37,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_PROC
......@@ -46,6 +47,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_DATA
......@@ -57,6 +59,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_CODE
......
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
View file @ 64c672ae
......@@ -37,6 +37,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_PROC
......@@ -46,6 +47,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_DATA
......@@ -57,6 +59,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_CODE
......
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
View file @ 64c672ae
......@@ -37,6 +37,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_PROC
......@@ -46,6 +47,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_DATA
......@@ -57,6 +59,7 @@
#include "host.fuc"
#include "memx.fuc"
#include "perf.fuc"
#include "i2c_.fuc"
#include "test.fuc"
#include "idle.fuc"
#undef INCLUDE_CODE
......
drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
View file @ 64c672ae
......@@ -7,6 +7,7 @@
#define PROC_HOST 0x54534f48
#define PROC_MEMX 0x584d454d
#define PROC_PERF 0x46524550
#define PROC_I2C_ 0x5f433249
#define PROC_TEST 0x54534554
/* KERN: message identifiers */
......@@ -24,4 +25,22 @@
#define MEMX_WAIT 3
#define MEMX_DELAY 4
/* I2C_: message identifiers */
#define I2C__MSG_RD08 0
#define I2C__MSG_WR08 1
#define I2C__MSG_DATA0_PORT 24:31
#define I2C__MSG_DATA0_ADDR 14:23
#define I2C__MSG_DATA0_RD08_PORT I2C__MSG_DATA0_PORT
#define I2C__MSG_DATA0_RD08_ADDR I2C__MSG_DATA0_ADDR
#define I2C__MSG_DATA0_RD08_REG 0:7
#define I2C__MSG_DATA1_RD08_VAL 0:7
#define I2C__MSG_DATA0_WR08_PORT I2C__MSG_DATA0_PORT
#define I2C__MSG_DATA0_WR08_ADDR I2C__MSG_DATA0_ADDR
#define I2C__MSG_DATA0_WR08_SYNC 8:8
#define I2C__MSG_DATA0_WR08_REG 0:7
#define I2C__MSG_DATA1_WR08_VAL 0:7
#endif
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