Commit 6636dc5e authored by Will Deacon's avatar Will Deacon Committed by Greg Kroah-Hartman

arm64: io: Ensure value passed to __iormb() is held in a 64-bit register

[ Upstream commit 1b57ec8c ]

As of commit 6460d320 ("arm64: io: Ensure calls to delay routines
are ordered against prior readX()"), MMIO reads smaller than 64 bits
fail to compile under clang because we end up mixing 32-bit and 64-bit
register operands for the same data processing instruction:

./include/asm-generic/io.h:695:9: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths]
        return readb(addr);
               ^
./arch/arm64/include/asm/io.h:147:58: note: expanded from macro 'readb'
                                                                       ^
./include/asm-generic/io.h:695:9: note: use constraint modifier "w"
./arch/arm64/include/asm/io.h:147:50: note: expanded from macro 'readb'
                                                               ^
./arch/arm64/include/asm/io.h:118:24: note: expanded from macro '__iormb'
        asm volatile("eor       %0, %1, %1\n"                           \
                                    ^

Fix the build by casting the macro argument to 'unsigned long' when used
as an input to the inline asm.
Reported-by: default avatarNick Desaulniers <nick.desaulniers@gmail.com>
Reported-by: default avatarNathan Chancellor <natechancellor@gmail.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent e6ee8bfc
...@@ -119,7 +119,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) ...@@ -119,7 +119,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
*/ \ */ \
asm volatile("eor %0, %1, %1\n" \ asm volatile("eor %0, %1, %1\n" \
"cbnz %0, ." \ "cbnz %0, ." \
: "=r" (tmp) : "r" (v) : "memory"); \ : "=r" (tmp) : "r" ((unsigned long)(v)) \
: "memory"); \
}) })
#define __iowmb() wmb() #define __iowmb() wmb()
......
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