drm/amd/display: Add DPIA NOTIFICATION logic

[WHY]
Adding the new DPIA NOTIFY packets from DMUB
As per the design with Cruise to account for
250ms response delay otherwise

[HOW]
Added th DPIA NOTIFY logic as per DMUB logic
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_stat.c

@@ -65,6 +65,7 @@ void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification
 	/* For HPD/HPD RX, convert dpia port index into link index */
 	if (notify->type == DMUB_NOTIFICATION_HPD ||
 	    notify->type == DMUB_NOTIFICATION_HPD_IRQ ||
+		notify->type == DMUB_NOTIFICATION_DPIA_NOTIFICATION ||
 	    notify->type == DMUB_NOTIFICATION_SET_CONFIG_REPLY) {
 		notify->link_index =
 			get_link_index_from_dpia_port_index(dc, notify->link_index);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

@@ -126,6 +126,7 @@ enum dmub_notification_type {
 	DMUB_NOTIFICATION_HPD,
 	DMUB_NOTIFICATION_HPD_IRQ,
 	DMUB_NOTIFICATION_SET_CONFIG_REPLY,
+	DMUB_NOTIFICATION_DPIA_NOTIFICATION,
 	DMUB_NOTIFICATION_MAX
 };
 
@@ -453,6 +454,7 @@ struct dmub_srv {
  * @pending_notification: Indicates there are other pending notifications
  * @aux_reply: aux reply
  * @hpd_status: hpd status
+ * @bw_alloc_reply: BW Allocation reply from CM/DPIA
  */
 struct dmub_notification {
 	enum dmub_notification_type type;
@@ -463,6 +465,7 @@ struct dmub_notification {
 		struct aux_reply_data aux_reply;
 		enum dp_hpd_status hpd_status;
 		enum set_config_status sc_status;
+		struct dpia_notification_reply_data bw_alloc_reply;
 	};
 };
 

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

@@ -770,6 +770,7 @@ enum dmub_out_cmd_type {
 	 * Command type used for SET_CONFIG Reply notification
 	 */
 	DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
+	DMUB_OUT_CMD__DPIA_NOTIFICATION = 5
 };
 
 /* DMUB_CMD__DPIA command sub-types. */
@@ -1516,6 +1517,84 @@ struct dp_hpd_data {
 	uint8_t pad;
 };
 
+/**
+ * DPIA NOTIFICATION Response Type
+ */
+enum dpia_notify_bw_alloc_status {
+
+	DPIA_BW_REQ_FAILED = 0,
+	DPIA_BW_REQ_SUCCESS,
+	DPIA_EST_BW_CHANGED,
+	DPIA_BW_ALLOC_CAPS_CHANGED
+};
+
+/* DMUB_OUT_CMD__DPIA_NOTIFY Reply command - OutBox Cmd */
+/**
+ * Data passed to driver from FW in a DMUB_OUT_CMD__DPIA_NOTIFY command.
+ */
+struct dpia_notification_reply_data {
+	uint8_t allocated_bw;
+	uint8_t estimated_bw;
+};
+
+struct dpia_notification_common {
+	bool shared;
+};
+
+struct dpia_bw_allocation_notify_data {
+	union {
+		struct {
+			uint16_t cm_bw_alloc_support: 1;	/**< USB4 CM BW Allocation mode support */
+			uint16_t bw_request_failed: 1;		/**< BW_Request_Failed */
+			uint16_t bw_request_succeeded: 1;	/**< BW_Request_Succeeded */
+			uint16_t est_bw_changed: 1;			/**< Estimated_BW changed */
+			uint16_t bw_alloc_cap_changed: 1;	/**< BW_Allocation_Capabiity_Changed */
+			uint16_t reserved: 11;
+		} bits;
+		uint16_t flags;
+	};
+	uint8_t cm_id;			/**< CM ID */
+	uint8_t group_id;		/**< Group ID */
+	uint8_t granularity;	/**< BW Allocation Granularity */
+	uint8_t estimated_bw;	/**< Estimated_BW */
+	uint8_t allocated_bw;	/**< Allocated_BW */
+	uint8_t reserved;
+};
+
+union dpia_notification_data {
+	struct dpia_notification_common common_data;
+	struct dpia_bw_allocation_notify_data dpia_bw_alloc;	/**< Used for DPIA BW Allocation mode notification */
+};
+
+enum dmub_cmd_dpia_notification_type {
+	DPIA_NOTIFY__BW_ALLOCATION = 0,
+};
+
+struct dpia_notification_header {
+	uint8_t instance;							/**< DPIA Instance */
+	uint8_t reserved[3];
+	enum dmub_cmd_dpia_notification_type type;	/**< DPIA notification type */
+};
+
+struct dpia_notification_payload {
+	struct dpia_notification_header  header;
+	union dpia_notification_data      data;   /**< DPIA notification data */
+};
+
+/**
+ * Definition of a DMUB_OUT_CMD__DPIA_NOTIFY command.
+ */
+struct dmub_rb_cmd_dpia_notification {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;  /**< DPIA notification header */
+	/**
+	 * Data passed to driver from FW in a DMUB_OUT_CMD__DPIA_NOTIFY command.
+	 */
+	struct dpia_notification_payload payload; /**< DPIA notification payload */
+};
+
 /**
  * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
  */
@@ -3422,6 +3501,10 @@ union dmub_rb_out_cmd {
 	 * SET_CONFIG reply command.
 	 */
 	struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
+	/**
+	 * BW ALLOCATION notification command.
+	 */
+	struct dmub_rb_cmd_dpia_notification dpia_notify;
 };
 #pragma pack(pop)
 

drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c

@@ -92,6 +92,27 @@ enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,
 		notify->link_index = cmd.set_config_reply.set_config_reply_control.instance;
 		notify->sc_status = cmd.set_config_reply.set_config_reply_control.status;
 		break;
+	case DMUB_OUT_CMD__DPIA_NOTIFICATION:
+		notify->type = DMUB_NOTIFICATION_DPIA_NOTIFICATION;
+		notify->link_index = cmd.dpia_notify.payload.header.instance;
+
+		if (cmd.dpia_notify.payload.header.type == DPIA_NOTIFY__BW_ALLOCATION) {
+
+			if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_failed) {
+				notify->result = DPIA_BW_REQ_FAILED;
+			} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_succeeded) {
+				notify->result = DPIA_BW_REQ_SUCCESS;
+				notify->bw_alloc_reply.allocated_bw =
+						cmd.dpia_notify.payload.data.dpia_bw_alloc.allocated_bw;
+			} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.est_bw_changed) {
+				notify->result = DPIA_EST_BW_CHANGED;
+				notify->bw_alloc_reply.estimated_bw =
+						cmd.dpia_notify.payload.data.dpia_bw_alloc.estimated_bw;
+			} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_alloc_cap_changed) {
+				notify->result = DPIA_BW_ALLOC_CAPS_CHANGED;
+			}
+		}
+		break;
 	default:
 		notify->type = DMUB_NOTIFICATION_NO_DATA;
 		break;