Commit 66a89509 authored by Stephen Boyd's avatar Stephen Boyd Committed by David Brown

ARM: msm: Don't touch GIC registers outside of GIC code

The MSM code has some antiquated register writes to set up the
PPIs to be edge triggered. Now that we have the percpu irq
interface we don't need this code so let's remove it and update
the percpu irq user (msm_timer) to set the irq type.
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarDavid Brown <davidb@codeaurora.org>
parent e8ea1ea9
...@@ -55,24 +55,11 @@ static void __init msm8960_map_io(void) ...@@ -55,24 +55,11 @@ static void __init msm8960_map_io(void)
static void __init msm8960_init_irq(void) static void __init msm8960_init_irq(void)
{ {
unsigned int i;
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE); (void *)MSM_QGIC_CPU_BASE);
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
if (machine_is_msm8960_rumi3()) if (machine_is_msm8960_rumi3())
writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
* as they are configured as level, which does not play nice with
* handle_percpu_irq.
*/
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
irq_set_handler(i, handle_percpu_irq);
}
} }
static struct platform_device *sim_devices[] __initdata = { static struct platform_device *sim_devices[] __initdata = {
......
...@@ -67,9 +67,6 @@ static void __init msm8x60_init_irq(void) ...@@ -67,9 +67,6 @@ static void __init msm8x60_init_irq(void)
of_irq_init(msm_dt_gic_match); of_irq_init(msm_dt_gic_match);
#endif #endif
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
/* RUMI does not adhere to GIC spec by enabling STIs by default. /* RUMI does not adhere to GIC spec by enabling STIs by default.
* Enable/clear is supposed to be RO for STIs, but is RW on RUMI. * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
*/ */
......
...@@ -22,17 +22,12 @@ ...@@ -22,17 +22,12 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
#include <mach/msm_iomap.h>
#include "scm-boot.h" #include "scm-boot.h"
#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
#define SCSS_CPU1CORE_RESET 0xD80 #define SCSS_CPU1CORE_RESET 0xD80
#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
#define GIC_PPI_EDGE_MASK 0xFFFFD7FF
extern void msm_secondary_startup(void); extern void msm_secondary_startup(void);
/* /*
* control for which core is the next to come out of the secondary * control for which core is the next to come out of the secondary
...@@ -50,9 +45,6 @@ static inline int get_core_count(void) ...@@ -50,9 +45,6 @@ static inline int get_core_count(void)
void __cpuinit platform_secondary_init(unsigned int cpu) void __cpuinit platform_secondary_init(unsigned int cpu)
{ {
/* Configure edge-triggered PPIs */
writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
/* /*
* if any interrupts are already enabled for the primary * if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled * core (e.g. timer irq), then they will not have been enabled
......
...@@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) ...@@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
*__this_cpu_ptr(msm_evt.percpu_evt) = evt; *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
clockevents_register_device(evt); clockevents_register_device(evt);
enable_percpu_irq(evt->irq, 0); enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
return 0; return 0;
} }
...@@ -219,7 +219,7 @@ static void __init msm_timer_init(void) ...@@ -219,7 +219,7 @@ static void __init msm_timer_init(void)
res = request_percpu_irq(ce->irq, msm_timer_interrupt, res = request_percpu_irq(ce->irq, msm_timer_interrupt,
ce->name, msm_evt.percpu_evt); ce->name, msm_evt.percpu_evt);
if (!res) { if (!res) {
enable_percpu_irq(ce->irq, 0); enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_LOCAL_TIMERS #ifdef CONFIG_LOCAL_TIMERS
local_timer_register(&msm_local_timer_ops); local_timer_register(&msm_local_timer_ops);
#endif #endif
......
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